forked from OSchip/llvm-project
170 lines
6.1 KiB
LLVM
170 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; INCP
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define i64 @cntp_add_nxv16i1(i64 %x, <vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_add_nxv16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: incp x0, p0.b
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %1, <vscale x 16 x i1> %pg)
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%add = add i64 %2, %x
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ret i64 %add
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}
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define i64 @cntp_add_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_add_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: incp x0, p0.h
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %1, <vscale x 8 x i1> %pg)
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%add = add i64 %2, %x
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ret i64 %add
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}
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define i64 @cntp_add_nxv4i1(i64 %x, <vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_add_nxv4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: incp x0, p0.s
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %pg)
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%add = add i64 %2, %x
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ret i64 %add
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}
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define i64 @cntp_add_nxv2i1(i64 %x, <vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_add_nxv2i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: incp x0, p0.d
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
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%add = add i64 %2, %x
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ret i64 %add
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}
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define i64 @cntp_add_all_active_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_add_all_active_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: incp x0, p0.h
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%2 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
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%3 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %pg)
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%add = add i64 %3, %x
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ret i64 %add
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}
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define i64 @cntp_add_nxv2i1_oneuse(i64 %x, <vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_add_nxv2i1_oneuse:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: cntp x8, p1, p0.d
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; CHECK-NEXT: add x9, x8, x0
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; CHECK-NEXT: madd x0, x8, x0, x9
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
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%add = add i64 %2, %x
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%mul = mul i64 %2, %x
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%res = add i64 %add, %mul
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ret i64 %res
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}
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; DECP
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define i64 @cntp_sub_nxv16i1(i64 %x, <vscale x 16 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_sub_nxv16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: decp x0, p0.b
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %1, <vscale x 16 x i1> %pg)
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%sub = sub i64 %x, %2
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ret i64 %sub
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}
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define i64 @cntp_sub_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_sub_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: decp x0, p0.h
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %1, <vscale x 8 x i1> %pg)
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%sub = sub i64 %x, %2
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ret i64 %sub
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}
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define i64 @cntp_sub_nxv4i1(i64 %x, <vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_sub_nxv4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: decp x0, p0.s
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %1, <vscale x 4 x i1> %pg)
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%sub = sub i64 %x, %2
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ret i64 %sub
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}
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define i64 @cntp_sub_nxv2i1(i64 %x, <vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_sub_nxv2i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: decp x0, p0.d
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
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%sub = sub i64 %x, %2
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ret i64 %sub
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}
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define i64 @cntp_sub_all_active_nxv8i1(i64 %x, <vscale x 8 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_sub_all_active_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: decp x0, p0.h
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%2 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %1)
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%3 = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %2, <vscale x 8 x i1> %pg)
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%sub = sub i64 %x, %3
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ret i64 %sub
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}
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define i64 @cntp_sub_nxv2i1_multiuse(i64 %x, <vscale x 2 x i1> %pg) #0 {
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; CHECK-LABEL: cntp_sub_nxv2i1_multiuse:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: cntp x8, p1, p0.d
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; CHECK-NEXT: sub x9, x8, x0
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; CHECK-NEXT: madd x0, x8, x0, x9
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%2 = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %1, <vscale x 2 x i1> %pg)
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%add = sub i64 %2, %x
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%mul = mul i64 %2, %x
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%res = add i64 %add, %mul
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ret i64 %res
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}
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declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
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declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
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declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
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declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
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attributes #0 = { "target-features"="+sve" }
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