forked from OSchip/llvm-project
32 lines
870 B
LLVM
32 lines
870 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -O3 < %s | FileCheck %s
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; This used to miscompile:
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; The 16-bit -1 should not become 32-bit -1 (sub w8, w8, #1).
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@g = global i16 0, align 4
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define i32 @srl_and() {
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; CHECK-LABEL: srl_and:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, :got:g
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; CHECK-NEXT: mov w9, #50
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; CHECK-NEXT: ldr x8, [x8, :got_lo12:g]
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; CHECK-NEXT: ldrh w8, [x8]
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; CHECK-NEXT: eor w8, w8, w9
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; CHECK-NEXT: mov w9, #65535
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: and w0, w8, w8, lsr #16
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; CHECK-NEXT: ret
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entry:
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%0 = load i16, i16* @g, align 4
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%1 = xor i16 %0, 50
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%tobool = icmp ne i16 %1, 0
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%lor.ext = zext i1 %tobool to i32
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%sub = add i16 %1, -1
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%srl = zext i16 %sub to i32
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%and = and i32 %srl, %lor.ext
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ret i32 %and
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}
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