Pete Cooper 8bbce768d8 Move X86::VCVTTSD2SIrr from the 2 operand to 1 operand MemRegOp table. ... Can someone with more knowledge of this please look at other entries to see if others need moved. llvm-svn: 158474		2012-06-14 22:12:58 +00:00
clang	Still more Doxygen documentation fixes:	2012-06-14 21:40:34 +00:00
compiler-rt	tsan: fix COMPAT mapping to not produce false reports	2012-06-14 21:40:35 +00:00
debuginfo-tests	Fix this for buggy gdb behavior alongside the change	2012-06-05 18:16:03 +00:00
libclc	configure.py: Add an install rule.	2012-06-01 17:29:59 +00:00
libcxx	Revert pair constructors back to using is_convertible instead of is_constructible. This should pull things into alignment with the final draft. Fixes http://llvm.org/bugs/show_bug.cgi?id=13063#add_comment.	2012-06-09 20:01:23 +00:00
libcxxabi	Fix bug in cxa_demangle involving template substitution.	2012-05-02 15:38:11 +00:00
lld	flesh out mach-o Reference Kinds	2012-06-12 23:01:30 +00:00
lldb	rdar://problem/11390100	2012-06-11 21:05:26 +00:00
llvm	Move X86::VCVTTSD2SIrr from the 2 operand to 1 operand MemRegOp table.	2012-06-14 22:12:58 +00:00
polly	Add some tests for the independent blocks pass.	2012-06-11 10:25:12 +00:00