llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops
Sam Parker 173de03740 [ARM][LowOverheadLoops] Revert after read/write
Currently we check whether LR is stored/loaded to/from inbetween the
loop decrement and loop end pseudo instructions. There's two problems
here:
- It relies on all load/store instructions being labelled as such in
  tablegen.
- Actually any use of loop decrement is troublesome because the value
  doesn't exist!
    
So we need to check for any read/write of LR that occurs between the
two instructions and revert if we find anything.

Differential Revision: https://reviews.llvm.org/D65792

llvm-svn: 368130
2019-08-07 07:39:19 +00:00
..
branch-targets.ll [ARM][LowOverheadLoops] Fix branch target codegen 2019-07-23 14:08:46 +00:00
cond-mov.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
end-positive-offset.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
loop-guards.ll
massive.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
multiblock-massive.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
revert-after-call.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
revert-after-read.mir [ARM][LowOverheadLoops] Revert after read/write 2019-08-07 07:39:19 +00:00
revert-after-spill.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
revert-after-write.mir [ARM][LowOverheadLoops] Revert after read/write 2019-08-07 07:39:19 +00:00
revert-non-header.mir [ARM][LowOverheadLoops] Revert non-header LE target 2019-07-30 08:08:44 +00:00
revert-non-loop.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
revert-while.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
size-limit.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
switch.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
while-negative-offset.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00
while.mir [ARM][LowOverheadLoops] Add CPSR defs 2019-07-26 08:15:01 +00:00