forked from OSchip/llvm-project
166 lines
5.6 KiB
LLVM
166 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -O3 -S | FileCheck %s
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; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
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; This is based on the following most basic C++ code:
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;
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; struct S {
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; int* data;
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; int x, y, z;
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; };
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;
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; S gen(S a) {
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; S b;
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; b.data = a.data;
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; return b;
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; }
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;
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; void escape0(S);
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;
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; int* foo(S a) {
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; S b = gen(a);
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; escape0(b);
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; return b.data;
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; }
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;
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; int cond();
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; void sync0();
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; void sync1();
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; void escape0(int*);
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; void escape1(int*);
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;
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; int* bar(S a) {
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; S b = gen(a);
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; if(cond()) {
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; sync0();
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; escape0(b.data);
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; } else {
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; sync1();
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; escape1(b.data);
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; }
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; return b.data;
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; }
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;
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; There are no inttoptr casts in the original source code, nor should there be any in the optimized IR.
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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%0 = type { i32*, i32, i32, i32 }
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define dso_local void @_Z3gen1S(%0* noalias sret(%0) align 8 %arg, %0* byval(%0) align 8 %arg1) {
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; CHECK-LABEL: @_Z3gen1S(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[ARG1:%.*]], i64 0, i32 0
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; CHECK-NEXT: [[I2:%.*]] = load i32*, i32** [[I]], align 8
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; CHECK-NEXT: [[I3:%.*]] = getelementptr inbounds [[TMP0]], %0* [[ARG:%.*]], i64 0, i32 0
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; CHECK-NEXT: store i32* [[I2]], i32** [[I3]], align 8
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; CHECK-NEXT: ret void
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;
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bb:
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%i = getelementptr inbounds %0, %0* %arg1, i32 0, i32 0
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%i2 = load i32*, i32** %i, align 8
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%i3 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0
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store i32* %i2, i32** %i3, align 8
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ret void
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}
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define dso_local i32* @_Z3foo1S(%0* byval(%0) align 8 %arg) {
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; CHECK-LABEL: @_Z3foo1S(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[I2:%.*]] = alloca [[TMP0:%.*]], align 8
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; CHECK-NEXT: [[I1_SROA_0_0_I5_SROA_IDX:%.*]] = getelementptr inbounds [[TMP0]], %0* [[ARG:%.*]], i64 0, i32 0
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; CHECK-NEXT: [[I1_SROA_0_0_COPYLOAD:%.*]] = load i32*, i32** [[I1_SROA_0_0_I5_SROA_IDX]], align 8
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; CHECK-NEXT: [[I_SROA_0_0_I6_SROA_IDX:%.*]] = getelementptr inbounds [[TMP0]], %0* [[I2]], i64 0, i32 0
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; CHECK-NEXT: store i32* [[I1_SROA_0_0_COPYLOAD]], i32** [[I_SROA_0_0_I6_SROA_IDX]], align 8
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; CHECK-NEXT: tail call void @_Z7escape01S(%0* nonnull byval(%0) align 8 [[I2]])
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; CHECK-NEXT: ret i32* [[I1_SROA_0_0_COPYLOAD]]
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;
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bb:
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%i = alloca %0, align 8
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%i1 = alloca %0, align 8
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%i2 = alloca %0, align 8
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%i3 = bitcast %0* %i to i8*
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call void @llvm.lifetime.start.p0i8(i64 24, i8* %i3)
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%i4 = bitcast %0* %i1 to i8*
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%i5 = bitcast %0* %arg to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i4, i8* align 8 %i5, i64 24, i1 false)
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call void @_Z3gen1S(%0* sret(%0) align 8 %i, %0* byval(%0) align 8 %i1)
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%i6 = bitcast %0* %i2 to i8*
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%i7 = bitcast %0* %i to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i6, i8* align 8 %i7, i64 24, i1 false)
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call void @_Z7escape01S(%0* byval(%0) align 8 %i2)
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%i8 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
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%i9 = load i32*, i32** %i8, align 8
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%i10 = bitcast %0* %i to i8*
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call void @llvm.lifetime.end.p0i8(i64 24, i8* %i10)
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ret i32* %i9
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}
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declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
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declare dso_local void @_Z7escape01S(%0* byval(%0) align 8)
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declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
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define dso_local i32* @_Z3bar1S(%0* byval(%0) align 8 %arg) {
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; CHECK-LABEL: @_Z3bar1S(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[I1_SROA_0_0_I4_SROA_IDX:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[ARG:%.*]], i64 0, i32 0
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; CHECK-NEXT: [[I1_SROA_0_0_COPYLOAD:%.*]] = load i32*, i32** [[I1_SROA_0_0_I4_SROA_IDX]], align 8
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; CHECK-NEXT: [[I5:%.*]] = tail call i32 @_Z4condv()
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; CHECK-NEXT: [[I6_NOT:%.*]] = icmp eq i32 [[I5]], 0
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; CHECK-NEXT: br i1 [[I6_NOT]], label [[BB10:%.*]], label [[BB7:%.*]]
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; CHECK: bb7:
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; CHECK-NEXT: tail call void @_Z5sync0v()
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; CHECK-NEXT: tail call void @_Z7escape0Pi(i32* [[I1_SROA_0_0_COPYLOAD]])
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; CHECK-NEXT: br label [[BB13:%.*]]
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; CHECK: bb10:
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; CHECK-NEXT: tail call void @_Z5sync1v()
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; CHECK-NEXT: tail call void @_Z7escape1Pi(i32* [[I1_SROA_0_0_COPYLOAD]])
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; CHECK-NEXT: br label [[BB13]]
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; CHECK: bb13:
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; CHECK-NEXT: ret i32* [[I1_SROA_0_0_COPYLOAD]]
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;
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bb:
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%i = alloca %0, align 8
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%i1 = alloca %0, align 8
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%i2 = bitcast %0* %i to i8*
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call void @llvm.lifetime.start.p0i8(i64 24, i8* %i2)
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%i3 = bitcast %0* %i1 to i8*
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%i4 = bitcast %0* %arg to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i3, i8* align 8 %i4, i64 24, i1 false)
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call void @_Z3gen1S(%0* sret(%0) align 8 %i, %0* byval(%0) align 8 %i1)
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%i5 = call i32 @_Z4condv()
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%i6 = icmp ne i32 %i5, 0
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br i1 %i6, label %bb7, label %bb10
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bb7:
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call void @_Z5sync0v()
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%i8 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
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%i9 = load i32*, i32** %i8, align 8
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call void @_Z7escape0Pi(i32* %i9)
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br label %bb13
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bb10:
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call void @_Z5sync1v()
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%i11 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
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%i12 = load i32*, i32** %i11, align 8
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call void @_Z7escape1Pi(i32* %i12)
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br label %bb13
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bb13:
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%i14 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
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%i15 = load i32*, i32** %i14, align 8
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%i16 = bitcast %0* %i to i8*
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call void @llvm.lifetime.end.p0i8(i64 24, i8* %i16)
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ret i32* %i15
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}
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declare dso_local i32 @_Z4condv()
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declare dso_local void @_Z5sync0v()
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declare dso_local void @_Z7escape0Pi(i32*)
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declare dso_local void @_Z5sync1v()
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declare dso_local void @_Z7escape1Pi(i32*)
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