..
AArch64
GlobalISel: implement legalization pass, with just one transformation.
2016-07-22 20:03:43 +00:00
AMDGPU
Invariant start/end intrinsics overloaded for address space
2016-07-22 17:49:40 +00:00
ARM
[ARM] Skip inline asm memory operands in DAGToDAGISel
2016-07-20 09:48:24 +00:00
BPF
[BPF] Remove exit-on-error from tests (PR27768, PR27769)
2016-05-30 08:28:34 +00:00
Generic
Move mempcpy_call.ll to X86 subdirectory
2016-07-13 18:28:45 +00:00
Hexagon
[Hexagon] Use loop data prefetch on Hexagon
2016-07-22 14:22:43 +00:00
Inputs
…
Lanai
[lanai] Use peephole optimizer to generate more conditional ALU operations.
2016-07-07 23:36:04 +00:00
MIR
GlobalISel: implement alloca instruction
2016-07-22 16:59:52 +00:00
MSP430
…
Mips
[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
2016-07-22 07:18:33 +00:00
NVPTX
[NVPTX] Enable the load-store vectorizer on nvptx.
2016-07-20 22:11:36 +00:00
PowerPC
Revert "RegScavenging: Add scavengeRegisterBackwards()"
2016-07-20 00:21:32 +00:00
SPARC
VirtRegMap: Replace some identity copies with KILL instructions.
2016-07-09 00:19:07 +00:00
SystemZ
Revert "RegScavenging: Add scavengeRegisterBackwards()"
2016-07-20 00:21:32 +00:00
Thumb
Revert "RegScavenging: Add scavengeRegisterBackwards()"
2016-07-20 00:21:32 +00:00
Thumb2
[Thumb] Reapply r272251 with a fix for PR28348 (mk 2)
2016-07-05 12:37:13 +00:00
WebAssembly
[WebAssembly] Emit type signatures for declared functions
2016-06-03 18:34:36 +00:00
WinEH
revert http://reviews.llvm.org/D21101
2016-06-30 17:52:24 +00:00
X86
[SelectionDAG] Optimization of BITREVERSE legalization for power-of-2 integer scalar/vector types
2016-07-22 16:46:25 +00:00
XCore
IR: Introduce Module::global_objects().
2016-06-22 20:29:42 +00:00