forked from OSchip/llvm-project
40 lines
1.6 KiB
TableGen
40 lines
1.6 KiB
TableGen
//===- XCoreCallingConv.td - Calling Conventions for XCore -*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for XCore architecture.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// XCore Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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def RetCC_XCore : CallingConv<[
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// i32 are returned in registers R0, R1, R2, R3
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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// Integer values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32], CCAssignToStack<4, 4>>
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]>;
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//===----------------------------------------------------------------------===//
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// XCore Argument Calling Conventions
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//===----------------------------------------------------------------------===//
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def CC_XCore : CallingConv<[
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// Promote i8/i16 arguments to i32.
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// The 'nest' parameter, if any, is passed in R11.
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CCIfNest<CCAssignToReg<[R11]>>,
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// The first 4 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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// Integer values get stored in stack slots that are 4 bytes in
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// size and 4-byte aligned.
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CCIfType<[i32], CCAssignToStack<4, 4>>
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]>;
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