forked from OSchip/llvm-project
47 lines
1.7 KiB
TableGen
47 lines
1.7 KiB
TableGen
//===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the XCore target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Descriptions
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//===----------------------------------------------------------------------===//
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include "XCoreRegisterInfo.td"
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include "XCoreInstrInfo.td"
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include "XCoreCallingConv.td"
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def XCoreInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// XCore processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"xs1b-generic", []>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def XCore : Target {
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// Pull in Instruction Info:
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let InstructionSet = XCoreInstrInfo;
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}
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