Matt Arsenault fd02314113 AMDGPU: Start adding offset fields to flat instructions ... llvm-svn: 305194		2017-06-12 15:55:58 +00:00
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AArch64	[AArch64] Add fallback in FastISel fp16 conversions	2017-06-09 22:40:50 +00:00
AMDGPU	AMDGPU: Start adding offset fields to flat instructions	2017-06-12 15:55:58 +00:00
ARM	[ARM] Add scheduling info for VFMS	2017-06-09 09:19:09 +00:00
AVR	[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi	2017-05-31 06:27:46 +00:00
BPF	[bpf] fix a bug which causes incorrect big endian reloc fixup	2017-05-05 18:05:00 +00:00
Generic	CodeGen/LLVMTargetMachine: Refactor ISel pass construction; NFCI	2017-06-06 00:26:13 +00:00
Hexagon	[Hexagon] Skip mux generation when predicate register is undefined	2017-06-08 20:56:36 +00:00
Inputs	…
Lanai	CodeGen: Rename DEBUG_TYPE to match passnames	2017-05-25 21:26:32 +00:00
MIR	llc: Add ability to parse mir from stdin	2017-06-06 20:06:57 +00:00
MSP430	[MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex.	2017-05-24 15:08:30 +00:00
Mips	Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"	2017-06-09 14:37:08 +00:00
NVPTX	Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."	2017-05-18 18:50:05 +00:00
Nios2	[Nios2] Target registration	2017-05-29 09:48:30 +00:00
PowerPC	[PowerPC] add memcmp test with one constant operand and equality cmp; NFC	2017-06-09 23:15:14 +00:00
SPARC	Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."	2017-05-18 18:50:05 +00:00
SystemZ	[SystemZ] Simplify test case. NFC	2017-06-02 23:40:58 +00:00
Thumb	Move machine-cse-physreg.mir to test/CodeGen/Thumb	2017-05-24 17:20:47 +00:00
Thumb2	MIR: remove explicit "noVRegs" property.	2017-05-30 21:28:57 +00:00
WebAssembly	[wasm] Fix test after r304117.	2017-05-29 16:32:52 +00:00
WinEH	…
X86	StackColoring: smarter check for slot overlap	2017-06-12 14:56:02 +00:00
XCore	AsmPrinter: mark the beginning and the end of a function in verbose mode	2017-05-23 21:22:16 +00:00