forked from OSchip/llvm-project
51 lines
1.7 KiB
YAML
51 lines
1.7 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
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---
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# Check for awareness that s_or_saveexec_b64 clobbers SCC
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#
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#CHECK: S_OR_SAVEEXEC_B64
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#CHECK: S_CMP_LT_I32
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#CHECK: S_CSELECT_B32
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name: test_wwm_scc
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_32, preferred-register: '' }
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- { id: 1, class: sgpr_32, preferred-register: '' }
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- { id: 2, class: sgpr_32, preferred-register: '' }
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- { id: 3, class: vgpr_32, preferred-register: '' }
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- { id: 4, class: vgpr_32, preferred-register: '' }
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- { id: 5, class: sgpr_32, preferred-register: '' }
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- { id: 6, class: vgpr_32, preferred-register: '' }
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- { id: 7, class: vgpr_32, preferred-register: '' }
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- { id: 8, class: sreg_32_xm0, preferred-register: '' }
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- { id: 9, class: sreg_32, preferred-register: '' }
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- { id: 10, class: sreg_32, preferred-register: '' }
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- { id: 11, class: vgpr_32, preferred-register: '' }
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- { id: 12, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '%sgpr0', virtual-reg: '%0' }
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- { reg: '%sgpr1', virtual-reg: '%1' }
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- { reg: '%sgpr2', virtual-reg: '%2' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: %sgpr0, %sgpr1, %sgpr2, %vgpr0
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%3 = COPY %vgpr0
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%2 = COPY %sgpr2
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%1 = COPY %sgpr1
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%0 = COPY %sgpr0
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S_CMP_LT_I32 0, %0, implicit-def %scc
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%12 = V_ADD_I32_e32 %3, %3, implicit-def %vcc, implicit %exec
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%5 = S_CSELECT_B32 %2, %1, implicit %scc
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%11 = V_ADD_I32_e32 %5, %12, implicit-def %vcc, implicit %exec
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%vgpr0 = WWM %11, implicit %exec
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SI_RETURN_TO_EPILOG %vgpr0
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...
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