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llvm-project/llvm/lib/Target/AMDGPU
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Matt Arsenault 9a19c240c0 AMDGPU: Materialize sign bits with bfrev 
If a constant is the same as the reverse of an inline immediate,
this is 4 bytes smaller than having to embed a 32-bit literal.

llvm-svn: 263201
 		2016-03-11 07:42:49 +00:00
..
AsmParser [AMDGPU] Assembler: Support DPP instructions. 2016-03-09 12:29:31 +00:00
Disassembler [AMDGPU] Fix SMEM instructions encoding/operand namings 2016-03-10 13:06:08 +00:00
InstPrinter Fix build error due to unsigned compare >= 0 in r263008 (NFC) 2016-03-09 14:58:23 +00:00
MCTargetDesc Remove autoconf support 2016-01-26 21:29:08 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
Utils fix sanitizer-ppc64be-linux failure for r262804 2016-03-06 15:13:54 +00:00
AMDGPU.h AMDGPU: Insert two S_NOP instructions for every high level source statement. 2016-03-03 03:53:29 +00:00
AMDGPU.td AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
AMDGPUAlwaysInlinePass.cpp AMDGPU: Minor cleanups to always inline pass 2015-07-13 19:08:36 +00:00
AMDGPUAnnotateKernelFeatures.cpp AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr 2016-01-30 05:10:59 +00:00
AMDGPUAnnotateUniformValues.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
AMDGPUAsmPrinter.cpp AMDGPU: Don't use estimated stack size when we know the real stack size 2016-03-01 04:58:20 +00:00
AMDGPUAsmPrinter.h AMDGPU: Emit note directive for HSA even if there are no functions 2016-01-12 17:18:17 +00:00
AMDGPUCallingConv.td AMDGPU/SI: Add support for non-void functions 2016-01-13 17:23:04 +00:00
AMDGPUFrameLowering.cpp AMDGPU: Fix old comments that mention AMDIL 2016-01-20 21:22:21 +00:00
AMDGPUFrameLowering.h AMDGPU: Create emergency stack slots during frame lowering 2015-11-06 18:17:45 +00:00
AMDGPUISelDAGToDAG.cpp AMDGPU: Simplify boolean conditional return statements 2016-03-02 23:00:21 +00:00
AMDGPUISelLowering.cpp AMDGPU: Move function only used by R600 2016-03-07 21:10:13 +00:00
AMDGPUISelLowering.h AMDGPU: Move function only used by R600 2016-03-07 21:10:13 +00:00
AMDGPUInstrInfo.cpp AMDGPU: Move subtarget specific code out of AMDGPUInstrInfo.cpp 2016-01-28 16:04:37 +00:00
AMDGPUInstrInfo.h AMDGPU: Remove some purely R600 functions from AMDGPUInstrInfo 2016-02-05 18:44:57 +00:00
AMDGPUInstrInfo.td AMDGPU: Rename intrinsic to better match instruction name 2016-02-13 01:03:00 +00:00
AMDGPUInstructions.td AMDGPU: Match more med3 integer patterns 2016-03-07 21:54:48 +00:00
AMDGPUIntrinsicInfo.cpp [llvm-tblgen] Avoid StringMatcher for GCC and MS builtin names 2016-01-27 01:43:12 +00:00
AMDGPUIntrinsicInfo.h
…
AMDGPUIntrinsics.td AMDGPU: Remove bfi and bfm intrinsics 2016-02-08 19:06:01 +00:00
AMDGPUMCInstLower.cpp Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC" 2016-02-22 20:49:58 +00:00
AMDGPUMCInstLower.h
…
AMDGPUMachineFunction.cpp AMDGPU/SI: Add getShaderType() function to Utils/ 2015-12-15 16:26:16 +00:00
AMDGPUMachineFunction.h AMDGPU/SI: Emit HSA kernels with symbol type STT_AMDGPU_HSA_KERNEL 2015-11-06 11:45:14 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp AMDGPU/SI: Remove assert from AMDGPUOpenCLImageTypeLowering pass 2015-10-01 21:16:05 +00:00
AMDGPUPromoteAlloca.cpp AMDGPU: Remove a fixme for ptrrtoint handling 2016-03-07 21:12:46 +00:00
AMDGPURegisterInfo.cpp
…
AMDGPURegisterInfo.h AMDGPU: Remove dead code 2015-09-19 06:41:10 +00:00
AMDGPURegisterInfo.td AMDGPU: Set SubRegIndex size and offset 2015-07-30 17:03:11 +00:00
AMDGPUSubtarget.cpp AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
AMDGPUSubtarget.h AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
AMDGPUTargetMachine.cpp AMDGPU: Insert two S_NOP instructions for every high level source statement. 2016-03-03 03:53:29 +00:00
AMDGPUTargetMachine.h AMDGPU: Fix ordering of CPU and FS parameters in TargetMachine constructors 2016-02-05 18:29:17 +00:00
AMDGPUTargetObjectFile.cpp AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA 2015-12-15 22:39:36 +00:00
AMDGPUTargetObjectFile.h AMDGPU/SI: Emit constant arrays in the .text section 2015-12-10 02:13:01 +00:00
AMDGPUTargetTransformInfo.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Override getCFInstrCost 2015-12-16 18:37:19 +00:00
AMDILCFGStructurizer.cpp Bug 20810: Use report_fatal_error instead of unreachable 2016-03-02 03:33:55 +00:00
AMDKernelCodeT.h [AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields) 2016-02-24 10:54:25 +00:00
CIInstructions.td [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target 2016-02-18 03:42:32 +00:00
CMakeLists.txt AMDGPU: Insert two S_NOP instructions for every high level source statement. 2016-03-03 03:53:29 +00:00
CaymanInstructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
EvergreenInstructions.td AMDGPU: Remove 24-bit intrinsics 2016-01-29 10:05:16 +00:00
LLVMBuild.txt [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target 2016-02-18 03:42:32 +00:00
Processors.td AMDGPU/SI: Stoney has only 16 LDS banks 2016-01-27 11:19:45 +00:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp CodeGen: Bring back MachineBasicBlock::iterator::getInstrIterator()... 2016-02-22 21:30:15 +00:00
R600Defines.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
…
R600ISelLowering.cpp AMDGPU: Move function only used by R600 2016-03-07 21:10:13 +00:00
R600ISelLowering.h AMDGPU: Move function only used by R600 2016-03-07 21:10:13 +00:00
R600InstrFormats.td
…
R600InstrInfo.cpp AMDGPU: Simplify boolean conditional return statements 2016-03-02 23:00:21 +00:00
R600InstrInfo.h CodeGen: TII: Take MachineInstr& in predicate API, NFC 2016-02-23 02:46:52 +00:00
R600Instructions.td AMDGPU: Rename intrinsic to better match instruction name 2016-02-13 01:03:00 +00:00
R600Intrinsics.td AMDGPU: Move AMDGPU intrinsics only used by R600 2016-01-26 04:49:24 +00:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600OptimizeVectorRegisters.cpp AMDGPU: Remove implicit ilist iterator conversions, NFC 2015-10-13 20:07:10 +00:00
R600Packetizer.cpp AMDGPU: Simplify boolean conditional return statements 2016-03-02 23:00:21 +00:00
R600RegisterInfo.cpp
…
R600RegisterInfo.h AMDGPU: Remove dead code 2015-09-19 06:41:10 +00:00
R600RegisterInfo.td
…
R600Schedule.td
…
R600TextureIntrinsicsReplacer.cpp AMDGPU: Rename some r600 intrinsics to use correct TargetPrefix 2016-01-22 19:00:09 +00:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
SIDefines.h [AMDGPU] Assembler: Support DPP instructions. 2016-03-09 12:29:31 +00:00
SIFixControlFlowLiveIntervals.cpp AMDGPU: Remove unused includes 2015-09-25 00:28:43 +00:00
SIFixSGPRCopies.cpp AMDGPU/SI: Fold operands with sub-registers 2016-01-07 17:10:29 +00:00
SIFixSGPRLiveRanges.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
SIFoldOperands.cpp AMDGPU: Fix passes depending on dominator tree for no reason 2016-02-11 06:15:34 +00:00
SIFrameLowering.cpp AMDGPU/SI: Don't try to move scratch wave offset when there are no free SGPRs 2016-03-03 03:45:09 +00:00
SIFrameLowering.h AMDGPU: Remove SIPrepareScratchRegs 2015-11-30 21:15:53 +00:00
SIISelLowering.cpp AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
SIISelLowering.h AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
SIInsertNopsPass.cpp AMDGPU: Insert two S_NOP instructions for every high level source statement. 2016-03-03 03:53:29 +00:00
SIInsertWaits.cpp AMDGPU: Simplify boolean conditional return statements 2016-03-02 23:00:21 +00:00
SIInstrFormats.td [AMDGPU] Fix SMEM instructions encoding/operand namings 2016-03-10 13:06:08 +00:00
SIInstrInfo.cpp [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC. 2016-03-09 16:00:35 +00:00
SIInstrInfo.h [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC. 2016-03-09 16:00:35 +00:00
SIInstrInfo.td [AMDGPU] Fix SMEM instructions encoding/operand namings 2016-03-10 13:06:08 +00:00
SIInstructions.td AMDGPU/SI: add llvm.amdgcn.buffer.load/store.format intrinsics 2016-03-10 18:43:50 +00:00
SIIntrinsics.td AMDGPU: Remove old sample intrinsics 2016-01-26 04:38:08 +00:00
SILoadStoreOptimizer.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
SILowerControlFlow.cpp AMDGPU: Set flat_scratch from flat_scratch_init reg 2016-02-12 06:31:30 +00:00
SILowerI1Copies.cpp AMDGPU: Fix passes depending on dominator tree for no reason 2016-02-11 06:15:34 +00:00
SIMachineFunctionInfo.cpp AMDGPU/SI: Add support for spiling SGPRs to scratch buffer 2016-03-04 18:31:18 +00:00
SIMachineFunctionInfo.h AMDGPU/SI: Add support for spiling SGPRs to scratch buffer 2016-03-04 18:31:18 +00:00
SIMachineScheduler.cpp [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC. 2016-03-09 16:00:35 +00:00
SIMachineScheduler.h RegisterPressure: Make liveness tracking subregister aware 2016-01-20 00:23:26 +00:00
SIRegisterInfo.cpp AMDGPU/SI: add llvm.amdgcn.buffer.load/store.format intrinsics 2016-03-10 18:43:50 +00:00
SIRegisterInfo.h AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserter 2016-03-04 18:02:01 +00:00
SIRegisterInfo.td AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
SISchedule.td TableGen: Check scheduling models for completeness 2016-03-01 20:03:21 +00:00
SIShrinkInstructions.cpp AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
SITypeRewriter.cpp AMDGPU/SI: Fix crash when inline assembly is used in a graphics shader 2016-01-06 22:01:04 +00:00
VIInstrFormats.td [AMDGPU] Fix SMEM instructions encoding/operand namings 2016-03-10 13:06:08 +00:00
VIInstructions.td [AMDGPU] Assembler: Support DPP instructions. 2016-03-09 12:29:31 +00:00