forked from OSchip/llvm-project
165 lines
6.6 KiB
LLVM
165 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+lzcnt | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=broadwell | FileCheck %s --check-prefix=CHECK --check-prefix=BROADWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=SKYLAKE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
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define i16 @test_ctlz_i16(i16 zeroext %a0, i16 *%a1) {
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; GENERIC-LABEL: test_ctlz_i16:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: lzcntw (%rsi), %cx
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; GENERIC-NEXT: lzcntw %di, %ax
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; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_ctlz_i16:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: lzcntw (%rsi), %cx # sched: [3:1.00]
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; HASWELL-NEXT: lzcntw %di, %ax # sched: [3:1.00]
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; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; HASWELL-NEXT: retq # sched: [2:1.00]
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;
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; BROADWELL-LABEL: test_ctlz_i16:
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; BROADWELL: # BB#0:
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; BROADWELL-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00]
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; BROADWELL-NEXT: lzcntw %di, %ax # sched: [3:1.00]
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; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; BROADWELL-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; BROADWELL-NEXT: retq # sched: [7:1.00]
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;
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; SKYLAKE-LABEL: test_ctlz_i16:
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; SKYLAKE: # BB#0:
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; SKYLAKE-NEXT: lzcntw (%rsi), %cx # sched: [8:1.00]
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; SKYLAKE-NEXT: lzcntw %di, %ax # sched: [3:1.00]
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; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; SKYLAKE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; SKYLAKE-NEXT: retq # sched: [7:1.00]
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;
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; BTVER2-LABEL: test_ctlz_i16:
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; BTVER2: # BB#0:
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; BTVER2-NEXT: lzcntw (%rsi), %cx
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; BTVER2-NEXT: lzcntw %di, %ax
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; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
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; BTVER2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_ctlz_i16:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: lzcntw (%rsi), %cx # sched: [6:0.50]
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; ZNVER1-NEXT: lzcntw %di, %ax # sched: [2:0.25]
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; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = load i16, i16 *%a1
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%2 = tail call i16 @llvm.ctlz.i16( i16 %1, i1 false )
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%3 = tail call i16 @llvm.ctlz.i16( i16 %a0, i1 false )
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%4 = or i16 %2, %3
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ret i16 %4
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}
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declare i16 @llvm.ctlz.i16(i16, i1)
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define i32 @test_ctlz_i32(i32 %a0, i32 *%a1) {
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; GENERIC-LABEL: test_ctlz_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: lzcntl (%rsi), %ecx
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; GENERIC-NEXT: lzcntl %edi, %eax
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; GENERIC-NEXT: orl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_ctlz_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: lzcntl (%rsi), %ecx # sched: [3:1.00]
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; HASWELL-NEXT: lzcntl %edi, %eax # sched: [3:1.00]
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; HASWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [2:1.00]
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;
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; BROADWELL-LABEL: test_ctlz_i32:
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; BROADWELL: # BB#0:
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; BROADWELL-NEXT: lzcntl (%rsi), %ecx # sched: [8:1.00]
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; BROADWELL-NEXT: lzcntl %edi, %eax # sched: [3:1.00]
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; BROADWELL-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; BROADWELL-NEXT: retq # sched: [7:1.00]
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;
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; SKYLAKE-LABEL: test_ctlz_i32:
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; SKYLAKE: # BB#0:
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; SKYLAKE-NEXT: lzcntl (%rsi), %ecx # sched: [8:1.00]
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; SKYLAKE-NEXT: lzcntl %edi, %eax # sched: [3:1.00]
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; SKYLAKE-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; SKYLAKE-NEXT: retq # sched: [7:1.00]
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;
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; BTVER2-LABEL: test_ctlz_i32:
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; BTVER2: # BB#0:
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; BTVER2-NEXT: lzcntl (%rsi), %ecx
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; BTVER2-NEXT: lzcntl %edi, %eax
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; BTVER2-NEXT: orl %ecx, %eax # sched: [1:0.50]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_ctlz_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: lzcntl (%rsi), %ecx # sched: [6:0.50]
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; ZNVER1-NEXT: lzcntl %edi, %eax # sched: [2:0.25]
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; ZNVER1-NEXT: orl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = load i32, i32 *%a1
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%2 = tail call i32 @llvm.ctlz.i32( i32 %1, i1 false )
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%3 = tail call i32 @llvm.ctlz.i32( i32 %a0, i1 false )
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%4 = or i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.ctlz.i32(i32, i1)
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define i64 @test_ctlz_i64(i64 %a0, i64 *%a1) {
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; GENERIC-LABEL: test_ctlz_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: lzcntq (%rsi), %rcx
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; GENERIC-NEXT: lzcntq %rdi, %rax
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; GENERIC-NEXT: orq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_ctlz_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: lzcntq (%rsi), %rcx # sched: [3:1.00]
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; HASWELL-NEXT: lzcntq %rdi, %rax # sched: [3:1.00]
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; HASWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [2:1.00]
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;
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; BROADWELL-LABEL: test_ctlz_i64:
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; BROADWELL: # BB#0:
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; BROADWELL-NEXT: lzcntq (%rsi), %rcx # sched: [8:1.00]
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; BROADWELL-NEXT: lzcntq %rdi, %rax # sched: [3:1.00]
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; BROADWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; BROADWELL-NEXT: retq # sched: [7:1.00]
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;
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; SKYLAKE-LABEL: test_ctlz_i64:
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; SKYLAKE: # BB#0:
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; SKYLAKE-NEXT: lzcntq (%rsi), %rcx # sched: [8:1.00]
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; SKYLAKE-NEXT: lzcntq %rdi, %rax # sched: [3:1.00]
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; SKYLAKE-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; SKYLAKE-NEXT: retq # sched: [7:1.00]
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;
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; BTVER2-LABEL: test_ctlz_i64:
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; BTVER2: # BB#0:
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; BTVER2-NEXT: lzcntq (%rsi), %rcx
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; BTVER2-NEXT: lzcntq %rdi, %rax
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; BTVER2-NEXT: orq %rcx, %rax # sched: [1:0.50]
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; BTVER2-NEXT: retq # sched: [4:1.00]
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;
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; ZNVER1-LABEL: test_ctlz_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: lzcntq (%rsi), %rcx # sched: [6:0.50]
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; ZNVER1-NEXT: lzcntq %rdi, %rax # sched: [2:0.25]
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; ZNVER1-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = load i64, i64 *%a1
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%2 = tail call i64 @llvm.ctlz.i64( i64 %1, i1 false )
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%3 = tail call i64 @llvm.ctlz.i64( i64 %a0, i1 false )
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%4 = or i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.ctlz.i64(i64, i1)
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