forked from OSchip/llvm-project
189 lines
7.0 KiB
LLVM
189 lines
7.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=ENABLED
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; RUN: llc --disable-x86-lea-opt < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=DISABLED
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%struct.anon1 = type { i32, i32, i32 }
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%struct.anon2 = type { i32, [32 x i32], i32 }
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@arr1 = external global [65 x %struct.anon1], align 16
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@arr2 = external global [65 x %struct.anon2], align 16
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define void @test1(i64 %x) nounwind {
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entry:
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%a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
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%tmp1 = load i32, i32* %b, align 4
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%sub = sub i32 %tmp, %tmp1
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%c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
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%tmp2 = load i32, i32* %c, align 4
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%add = add nsw i32 %sub, %tmp2
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %b, align 4
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store i32 222, i32* %c, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %b, align 4
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store i32 444, i32* %c, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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; CHECK-LABEL: test1:
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; CHECK: shlq $2, [[REG1:%[a-z]+]]
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; CHECK: movl arr1([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
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; CHECK: subl arr1+4([[REG1]],[[REG1]],2), {{.*}}
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; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
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; CHECK: addl arr1+8([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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}
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define void @test2(i64 %x) nounwind optsize {
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entry:
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%a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
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%tmp1 = load i32, i32* %b, align 4
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%sub = sub i32 %tmp, %tmp1
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%c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
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%tmp2 = load i32, i32* %c, align 4
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%add = add nsw i32 %sub, %tmp2
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %b, align 4
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store i32 222, i32* %c, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %b, align 4
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store i32 444, i32* %c, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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; CHECK-LABEL: test2:
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; CHECK: shlq $2, [[REG1:%[a-z]+]]
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; DISABLED: movl arr1([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: leaq arr1+4([[REG1]],[[REG1]],2), [[REG2:%[a-z]+]]
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; ENABLED: movl -4([[REG2]]), {{.*}}
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; ENABLED: subl ([[REG2]]), {{.*}}
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; ENABLED: addl 4([[REG2]]), {{.*}}
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; DISABLED: subl arr1+4([[REG1]],[[REG1]],2), {{.*}}
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; DISABLED: leaq arr1+8([[REG1]],[[REG1]],2), [[REG3:%[a-z]+]]
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; DISABLED: addl arr1+8([[REG1]],[[REG1]],2), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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}
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; Check that LEA optimization pass takes into account a resultant address
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; displacement when choosing a LEA instruction for replacing a redundant
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; address recalculation.
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define void @test3(i64 %x) nounwind optsize {
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entry:
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%a = getelementptr inbounds [65 x %struct.anon2], [65 x %struct.anon2]* @arr2, i64 0, i64 %x, i32 2
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon2], [65 x %struct.anon2]* @arr2, i64 0, i64 %x, i32 0
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%tmp1 = load i32, i32* %b, align 4
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%add = add nsw i32 %tmp, %tmp1
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %a, align 4
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store i32 222, i32* %b, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %a, align 4
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; Make sure the REG3's definition LEA won't be removed as redundant.
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%cvt = ptrtoint i32* %b to i32
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store i32 %cvt, i32* %b, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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; CHECK-LABEL: test3:
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; CHECK: imulq {{.*}}, [[REG1:%[a-z]+]]
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; CHECK: leaq arr2+132([[REG1]]), [[REG2:%[a-z]+]]
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; CHECK: leaq arr2([[REG1]]), [[REG3:%[a-z]+]]
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; REG3's definition is closer to movl than REG2's, but the pass still chooses
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; REG2 because it provides the resultant address displacement fitting 1 byte.
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; ENABLED: movl ([[REG2]]), {{.*}}
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; ENABLED: addl ([[REG3]]), {{.*}}
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; DISABLED: movl arr2+132([[REG1]]), {{.*}}
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; DISABLED: addl arr2([[REG1]]), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; CHECK: movl {{.*}}, ([[REG3]])
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}
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define void @test4(i64 %x) nounwind minsize {
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entry:
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%a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
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%tmp1 = load i32, i32* %b, align 4
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%sub = sub i32 %tmp, %tmp1
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%c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
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%tmp2 = load i32, i32* %c, align 4
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%add = add nsw i32 %sub, %tmp2
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %b, align 4
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store i32 222, i32* %c, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %b, align 4
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store i32 444, i32* %c, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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; CHECK-LABEL: test4:
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; CHECK: imulq {{.*}}, [[REG1:%[a-z]+]]
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; DISABLED: movl arr1([[REG1]]), {{.*}}
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; CHECK: leaq arr1+4([[REG1]]), [[REG2:%[a-z]+]]
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; ENABLED: movl -4([[REG2]]), {{.*}}
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; ENABLED: subl ([[REG2]]), {{.*}}
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; ENABLED: addl 4([[REG2]]), {{.*}}
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; DISABLED: subl arr1+4([[REG1]]), {{.*}}
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; DISABLED: leaq arr1+8([[REG1]]), [[REG3:%[a-z]+]]
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; DISABLED: addl arr1+8([[REG1]]), {{.*}}
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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; CHECK: movl ${{[1-4]+}}, ([[REG2]])
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; ENABLED: movl ${{[1-4]+}}, 4([[REG2]])
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; DISABLED: movl ${{[1-4]+}}, ([[REG3]])
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}
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