forked from OSchip/llvm-project
186 lines
4.7 KiB
YAML
186 lines
4.7 KiB
YAML
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
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# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
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--- |
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define void @test_copy() {
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ret void
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}
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define void @test_copy2() {
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ret void
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}
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define void @test_copy3() {
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ret void
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}
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define void @test_copy4() {
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ret void
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}
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define void @test_copy5() {
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ret void
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}
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define void @test_copy6() {
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ret void
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}
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...
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---
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name: test_copy
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# ALL-LABEL: name: test_copy
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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# ALL-NEXT: - { id: 2, class: gr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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# ALL: %0:gr8 = COPY %al
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# ALL-NEXT: %2:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
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# ALL-NEXT: %1:gr32 = AND32ri8 %2, 1, implicit-def %eflags
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %eax
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%0(s1) = COPY %al
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%1(s32) = G_ZEXT %0(s1)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_copy2
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# ALL-LABEL: name: test_copy2
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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# ALL: %0:gr8 = COPY %al
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# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %eax
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%0(s8) = COPY %al
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%1(s32) = G_ZEXT %0(s8)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_copy3
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# ALL-LABEL: name: test_copy3
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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# ALL: %0:gr8 = COPY %al
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# ALL-NEXT: %1:gr32 = MOVZX32rr8 %0
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %eax
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%0(s8) = COPY %ax
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%1(s32) = G_ZEXT %0(s8)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_copy4
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# ALL-LABEL: name: test_copy4
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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# ALL: %0:gr16 = COPY %ax
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# ALL-NEXT: %1:gr32 = MOVZX32rr16 %0
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %eax
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%0(s16) = COPY %eax
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%1(s32) = G_ZEXT %0(s16)
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%eax = COPY %1(s32)
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RET 0, implicit %eax
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...
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---
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name: test_copy5
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# ALL-LABEL: name: test_copy5
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr8, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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# ALL: %0:gr8 = COPY %dl
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# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_8bit
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %eax,%edx
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%0(s8) = COPY %edx
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%eax = COPY %0(s8)
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RET 0, implicit %eax
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...
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---
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name: test_copy6
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# ALL-LABEL: name: test_copy6
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alignment: 4
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legalized: true
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regBankSelected: true
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# ALL: registers:
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# ALL-NEXT: - { id: 0, class: gr16, preferred-register: '' }
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# ALL-NEXT: - { id: 1, class: gr32, preferred-register: '' }
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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# ALL: %0:gr16 = COPY %dx
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# ALL-NEXT: %1:gr32 = SUBREG_TO_REG 0, %0, %subreg.sub_16bit
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# ALL-NEXT: %eax = COPY %1
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# ALL-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %eax,%edx
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%0(s16) = COPY %edx
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%eax = COPY %0(s16)
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RET 0, implicit %eax
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...
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