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llvm-project/llvm/test/CodeGen/RISCV
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Luis Marques 2e46312ffd [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting 
Some GEPs were not being split, presumably because that split would just be 
undone by the DAGCombiner. Not performing those splits can prevent important 
optimizations, such as preventing the element indices / member offsets from 
being (partially) folded into load/store instruction immediates. This patch:

- Makes the splits also occur in the cases where the base address and the GEP 
  are in the same BB.
- Ensures that the DAGCombiner doesn't reassociate them back again.

Differential Revision: https://reviews.llvm.org/D60294

llvm-svn: 363544
 		2019-06-17 10:54:12 +00:00
..
addc-adde-sube-subc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
addcarry.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
align.ll
…
alloca.ll
…
alu8.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
alu16.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
alu32.ll [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions 2019-01-12 07:32:31 +00:00
alu64.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
analyze-branch.ll
…
arith-with-overflow.ll [RISCV] Add tests for overflow intrinsics 2018-06-19 06:45:47 +00:00
atomic-cmpxchg-flag.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
atomic-cmpxchg.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
atomic-fence.ll [RISCV][NFC] Add CHECK lines for atomic operations on RV64I 2019-01-11 19:46:48 +00:00
atomic-load-store.ll [RISCV] Add codegen support for RV64A 2019-01-17 10:04:39 +00:00
atomic-rmw.ll [RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256 2019-06-15 07:49:14 +00:00
bare-select.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
blockaddress.ll
…
branch-relaxation.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
branch.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
byval.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
callee-saved-fpr32s.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
callee-saved-fpr64s.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
callee-saved-gprs.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
calling-conv-ilp32d.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
calling-conv-lp64.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
calling-conv-rv32f-ilp32.ll Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
calling-conv-sext-zext.ll
…
calls.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
codemodel-lowering.ll [RISCV] Implement adding a displacement to a BlockAddress 2019-04-05 08:40:57 +00:00
compress-inline-asm.ll
…
compress.ll
…
disable-tail-calls.ll [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
div.ll [RISCV] Introduce codegen patterns for RV64M-only instructions 2019-01-12 07:43:06 +00:00
double-arith.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
double-bitmanip-dagcombines.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
double-br-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-calling-conv.ll [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) 2019-03-30 09:15:47 +00:00
double-convert.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
double-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-frem.ll [RISCV] Mark FREM as Expand 2018-11-15 14:46:11 +00:00
double-imm.ll [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) 2019-03-30 09:15:47 +00:00
double-intrinsics.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
double-mem.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
double-previous-failure.ll [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x)) 2019-03-30 09:15:47 +00:00
double-select-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
double-stack-spill-restore.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
fixups-diff.ll [RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true 2018-08-16 11:26:37 +00:00
fixups-relax-diff.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
float-arith.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-bit-preserving-dagcombines.ll [RISCV] Support Bit-Preserving FP in F/D Extensions 2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-br-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
float-convert.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
float-frem.ll [RISCV] Mark FREM as Expand 2018-11-15 14:46:11 +00:00
float-imm.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
float-intrinsics.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
float-mem.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
float-select-fcmp.ll [RISCV] Add seto pattern expansion 2019-04-01 09:54:14 +00:00
flt-rounds.ll [SelectionDAG] Support result type promotion for FLT_ROUNDS_ 2018-11-30 13:18:33 +00:00
fp128.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
frame-info.ll [RISCV] Add CFI directives for RISCV prologue/epilog. 2019-06-12 03:04:22 +00:00
frame.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
frameaddr-returnaddr.ll [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands 2018-11-30 10:02:06 +00:00
get-setcc-result-type.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
hoist-global-addr-base.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
i32-icmp.ll [RISCV] Improve codegen for icmp {ne,eq} with a constant 2019-03-26 12:55:00 +00:00
imm-cse.ll
…
imm.ll Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI 2019-01-25 20:22:49 +00:00
indirectbr.ll [RISC-V] Fix a test case to not include label names as those aren't 2018-06-21 05:42:05 +00:00
init-array.ll [IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format 2019-05-15 02:35:32 +00:00
inline-asm-i-constraint-i1.ll [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll [RISCV][NFC] Add missing test file for D54093 2019-06-11 12:52:05 +00:00
inline-asm.ll [RISCV] Fix inline-asm.ll test by adding nounwind attribute 2019-06-12 05:32:30 +00:00
interrupt-attr-args-error.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-invalid.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-nocall.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
interrupt-attr-ret-error.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
jumptable.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
large-stack.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
legalize-fneg.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll [RISCV] Implement isLegalAddImmediate 2018-04-26 13:00:37 +00:00
mattr-invalid-combination.ll [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
mem.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
mem64.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
mul.ll [RISCV] Introduce codegen patterns for RV64M-only instructions 2019-01-12 07:43:06 +00:00
musttail-call.ll [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
option-norelax.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
option-norvc.ll [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
option-relax.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
option-rvc.ll [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
pic-models.ll [RISCV] Add lowering of addressing sequences for PIC 2019-06-11 12:57:47 +00:00
pr40333.ll [RISCV] Custom-legalise 32-bit variable shifts on RV64 2019-01-25 05:04:00 +00:00
prefetch.ll [SelectionDAG] Support promotion of PREFETCH operands 2018-11-30 10:06:31 +00:00
rem.ll [RISCV] Introduce codegen patterns for RV64M-only instructions 2019-01-12 07:43:06 +00:00
remat.ll [RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256 2019-06-15 07:49:14 +00:00
rotl-rotr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv32e.ll [RISCV] Add basic RV32E definitions and MC layer support 2019-03-22 11:21:40 +00:00
rv32i-rv64i-float-double.ll [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer 2019-03-13 16:33:45 +00:00
rv64d-double-convert.ll [RISCV] Implement RV64D codegen 2019-02-01 03:53:30 +00:00
rv64f-float-convert.ll [RISCV] Add RV64F codegen support 2019-01-31 22:48:38 +00:00
rv64i-exhaustive-w-insts.ll [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructions 2019-01-12 07:32:31 +00:00
rv64i-tricky-shifts.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv64m-exhaustive-w-insts.ll [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M 2019-01-25 05:11:34 +00:00
sdata-limit-0.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-4.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-limit-8.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
sdata-local-sym.ll [RISCV] Put data smaller than eight bytes to small data section 2019-04-11 04:59:13 +00:00
select-cc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
select-optimize-multiple.ll [RISCV] Optimize emission of SELECT sequences 2019-03-22 10:45:03 +00:00
select-optimize-multiple.mir [RISCV] Optimize emission of SELECT sequences 2019-03-22 10:45:03 +00:00
setcc-logic.ll [RISCV] Update setcc-logic.ll codegen test 2019-03-26 15:41:45 +00:00
sext-zext-trunc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll [RISCV] Eliminate unnecessary masking of promoted shift amounts 2018-10-12 23:18:52 +00:00
shifts.ll [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS 2019-04-16 14:38:32 +00:00
split-offsets.ll [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting 2019-06-17 10:54:12 +00:00
tail-calls.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
target-abi-invalid.ll [RISCV] Support -target-abi at the MC layer and for codegen 2019-03-09 09:28:06 +00:00
target-abi-valid.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
umulo-128-legalisation-lowering.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-16 13:56:23 +00:00
vararg.ll [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs 2019-03-30 17:59:30 +00:00
wide-mem.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
zext-with-load-is-free.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00