forked from OSchip/llvm-project
88 lines
3.5 KiB
LLVM
88 lines
3.5 KiB
LLVM
; FIXME: Need to add support for mubuf stores to enable this on SI.
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; XUN: llc < %s -march=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s
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; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=CI --check-prefix=GCN %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s
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; SMRD load with an immediate offset.
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; GCN-LABEL: {{^}}smrd0:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
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define amdgpu_kernel void @smrd0(i32 addrspace(4)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 1
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%1 = load i32, i32 addrspace(4)* %0
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store i32 %1, i32 addrspace(1)* undef
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ret void
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}
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; SMRD load with the largest possible immediate offset.
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; GCN-LABEL: {{^}}smrd1:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define amdgpu_kernel void @smrd1(i32 addrspace(4)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 255
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%1 = load i32, i32 addrspace(4)* %0
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store i32 %1, i32 addrspace(1)* undef
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate.
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; GCN-LABEL: {{^}}smrd2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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; GCN: s_endpgm
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define amdgpu_kernel void @smrd2(i32 addrspace(4)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 256
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%1 = load i32, i32 addrspace(4)* %0
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store i32 %1, i32 addrspace(1)* undef
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ret void
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}
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; SMRD load with a 64-bit offset
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; GCN-LABEL: {{^}}smrd3:
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; FIXME: There are too many copies here because we don't fold immediates
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; through REG_SEQUENCE
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; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
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; TODO: Add VI checks
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; XGCN: s_endpgm
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define amdgpu_kernel void @smrd3(i32 addrspace(4)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 4294967296 ; 2 ^ 32
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%1 = load i32, i32 addrspace(4)* %0
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store i32 %1, i32 addrspace(1)* undef
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd4:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define amdgpu_kernel void @smrd4(i32 addrspace(4)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262143
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%1 = load i32, i32 addrspace(4)* %0
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store i32 %1, i32 addrspace(1)* undef
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd5:
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; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
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; GCN: s_endpgm
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define amdgpu_kernel void @smrd5(i32 addrspace(4)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262144
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%1 = load i32, i32 addrspace(4)* %0
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store i32 %1, i32 addrspace(1)* undef
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ret void
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}
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