forked from OSchip/llvm-project
87 lines
2.7 KiB
YAML
87 lines
2.7 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,SI
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,VI
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--- |
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define void @ashr(i32 addrspace(1)* %global0) {ret void}
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...
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---
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name: ashr
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legalized: true
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regBankSelected: true
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# GCN-LABEL: name: ashr
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
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; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:vgpr(s32) = COPY $vgpr0
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%3:vgpr(p1) = COPY $vgpr3_vgpr4
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; GCN: [[C1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
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; GCN: [[C4096:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
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%4:sgpr(s32) = G_CONSTANT i32 1
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%5:sgpr(s32) = G_CONSTANT i32 4096
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; ashr ss
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; GCN: [[SS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SGPR0]], [[SGPR1]]
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%6:sgpr(s32) = G_ASHR %0, %1
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; ashr si
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; GCN: [[SI:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SS]], [[C1]]
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%7:sgpr(s32) = G_ASHR %6, %4
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; ashr is
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; GCN: [[IS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[C1]], [[SI]]
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%8:sgpr(s32) = G_ASHR %4, %7
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; ashr sc
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; GCN: [[SC:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[IS]], [[C4096]]
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%9:sgpr(s32) = G_ASHR %8, %5
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; ashr cs
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; GCN: [[CS:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[C4096]], [[SC]]
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%10:sgpr(s32) = G_ASHR %5, %9
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; ashr vs
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; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[CS]], [[VGPR0]]
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%11:vgpr(s32) = G_ASHR %2, %10
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; ashr sv
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; SI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[CS]], [[VS]]
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; VI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VS]], [[CS]]
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%12:vgpr(s32) = G_ASHR %10, %11
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; ashr vv
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; SI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[SV]], [[VGPR0]]
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; VI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[VGPR0]], [[SV]]
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%13:vgpr(s32) = G_ASHR %12, %2
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; ashr iv
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; SI: [[IV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[C1]], [[VV]]
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; VI: [[IV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VV]], [[C1]]
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%14:vgpr(s32) = G_ASHR %4, %13
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; ashr vi
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; GCN: [[VI:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[C1]], [[IV]]
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%15:vgpr(s32) = G_ASHR %14, %4
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; ashr cv
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; SI: [[CV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[C4096]], [[VI]]
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; VI: [[CV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VI]], [[C4096]]
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%16:vgpr(s32) = G_ASHR %5, %15
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; ashr vc
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; GCN: [[VC:%[-1-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[C4096]], [[CV]]
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%17:vgpr(s32) = G_ASHR %16, %5
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G_STORE %17, %3 :: (store 4 into %ir.global0, addrspace 1)
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...
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---
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