llvm-project/llvm/test/Transforms/SLPVectorizer/AMDGPU
Craig Topper c195ae2f00 [SLPVectorizer][X86][AMDGPU] Remove fcmp+select to fmin/fmax reduction support.
Previously we could match fcmp+select to a reduction if the fcmp had
the nonans fast math flag. But if the select had the nonans fast
math flag, InstCombine would turn it into a fminnum/fmaxnum intrinsic
before SLP gets to it. Seems fairly likely that if one of the
fcmp+select pair have the fast math flag, they both would.

My plan is to start vectorizing the fmaxnum/fminnum version soon,
but I wanted to get this code out as it had some of the strangest
fast math flag behaviors.
2020-09-10 11:49:19 -07:00
..
add_sub_sat.ll AMDGPU: Make saturating add/sub legal for DAG path 2020-07-29 08:27:31 -04:00
address-space-ptr-sze-gep-index-assert.ll [NFC] GetUnderlyingObject -> getUnderlyingObject 2020-07-30 21:08:24 -07:00
bswap.ll
horizontal-store.ll [SLPVectorizer][X86][AMDGPU] Remove fcmp+select to fmin/fmax reduction support. 2020-09-10 11:49:19 -07:00
lit.local.cfg
packed-math.ll
reduction.ll [SLPVectorizer][X86][AMDGPU] Remove fcmp+select to fmin/fmax reduction support. 2020-09-10 11:49:19 -07:00
round.ll