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llvm-project/llvm/lib/Target/AArch64
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Pablo Barrio 642b21beba [AArch64] Enable RAS 1.1 system registers in all AArch64 
Some use cases (e.g. kernel devs) have strict requirements to only enable
features available with -march=armv8-a, e.g. no armv8.1-a. Enabling RAS 1.1 in
all AArch64 means they can consider to support it.

Bear in mind that the first versions of the Armv8 architecture still do not
support RAS 1.1. This patch only lets devs write code with the user-friendly
register mnemonic instead of the ugly generic S<op0>_<op1>_<Cn>_<Cm>_<op2>.
They still need to place runtime checks to make sure that the CPU to run on
supports RAS 1.1.

Differential Revision: https://reviews.llvm.org/D90594
 		2020-11-10 12:13:33 +00:00
..
AsmParser Revert "[AArch64][AsmParser] Remove 'x31' alias for 'sp/xzr' register." 2020-11-02 08:15:50 +00:00
Disassembler [AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB 2020-06-25 15:56:36 +01:00
GISel [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. 2020-11-05 11:18:11 -08:00
MCTargetDesc [AArch64] Implement .variant_pcs directive 2020-10-13 10:06:27 +00:00
TargetInfo
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Utils [ARM, AArch64] Fix a comment typo. NFC. 2020-08-06 09:23:45 +03:00
AArch64.h [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
AArch64.td [AArch64] Enable RAS 1.1 system registers in all AArch64 2020-11-10 12:13:33 +00:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp [AArch64] Update a code comment incorrectly referring to zero_reg. NFC 2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp hwasan: Support for outlined checks in the Linux kernel. 2020-10-30 14:25:40 -07:00
AArch64BranchTargets.cpp [AArch64] PAC/BTI code generation for LLVM generated functions 2020-09-25 11:47:14 +01:00
AArch64CallingConvention.cpp [SVE] Add fatal error when running out of registers for SVE tuple call arguments 2020-10-14 09:31:41 +01:00
AArch64CallingConvention.h
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AArch64CallingConvention.td [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp [CallSiteInfo] Handle bundles when updating call site info 2020-02-27 13:57:06 +01:00
AArch64CollectLOH.cpp [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg 2020-06-01 16:00:55 -07:00
AArch64Combine.td [GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x 2020-11-10 11:32:13 +01:00
AArch64CompressJumpTables.cpp
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AArch64CondBrTuning.cpp [AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14] 2020-04-22 17:03:40 -07:00
AArch64ConditionOptimizer.cpp MachineBasicBlock::updateTerminator now requires an explicit layout successor. 2020-06-06 22:30:51 -04:00
AArch64ConditionalCompares.cpp DomTree: Remove getChildren() accessor 2020-07-06 21:58:11 +02:00
AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp [SVE] Fix invalid assert in expand_DestructiveOp. 2020-07-04 09:21:40 +00:00
AArch64FalkorHWPFFix.cpp Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()" 2020-09-22 23:59:34 +03:00
AArch64FastISel.cpp [FastISel] update to use intrinsic's isCommutative(); NFC 2020-08-30 11:36:41 -04:00
AArch64FrameLowering.cpp [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
AArch64FrameLowering.h [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [AArch64][SVE] Fix umin/umax lowering to handle out of range imm. 2020-10-23 09:42:56 -07:00
AArch64ISelLowering.cpp [llvm][AArch64] Allow TB(N)Z to drop signext for sign bit tests. 2020-11-09 18:27:48 +00:00
AArch64ISelLowering.h [SVE][CodeGen] Lower scalable integer vector reductions 2020-11-04 11:38:49 +00:00
AArch64InstrAtomics.td
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AArch64InstrFormats.td [SVE][CodeGen] Lower scalable fp_extend & fp_round operations 2020-10-01 12:17:37 +01:00
AArch64InstrGISel.td [AArch64][GlobalISel] Add AArch64::G_DUPLANE[X] opcodes for lane duplicates. 2020-11-05 11:18:11 -08:00
AArch64InstrInfo.cpp [NFCI] Replace AArch64StackOffset by StackOffset. 2020-11-04 08:49:00 +00:00
AArch64InstrInfo.h [NFCI] Replace AArch64StackOffset by StackOffset. 2020-11-04 08:49:00 +00:00
AArch64InstrInfo.td [AArch64] Enable RAS 1.1 system registers in all AArch64 2020-11-10 12:13:33 +00:00
AArch64LoadStoreOptimizer.cpp [AArch64] Don't merge sp decrement into later stores when using WinCFI 2020-10-01 19:03:27 +03:00
AArch64MCInstLower.cpp
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AArch64MCInstLower.h
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AArch64MachineFunctionInfo.cpp [AArch64] PAC/BTI code generation for LLVM generated functions 2020-09-25 11:47:14 +01:00
AArch64MachineFunctionInfo.h [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64MacroFusion.cpp
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AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp [AArch64] Don't promote constants with float ConstantExpr. 2020-05-13 23:31:47 +01:00
AArch64RedundantCopyElimination.cpp
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference. 2020-11-05 11:02:18 +00:00
AArch64RegisterInfo.h [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long 2020-09-08 08:04:52 +01:00
AArch64RegisterInfo.td [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64SIMDInstrOpt.cpp [AArch64] reuse another map iterator. NFC 2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp [NFC] Clean up uses of MachineModuleInfoWrapperPass 2020-07-01 09:45:05 -07:00
AArch64SVEInstrInfo.td [SVE] Add ISel patterns for "insert undef_nxv#f##, f##, 0" 2020-10-13 10:49:18 +01:00
AArch64SchedA53.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA55.td [AArch64] Cortex-A55 scheduler model 2020-09-21 10:54:32 +01:00
AArch64SchedA57.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM3.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM4.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM5.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkor.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedTSV110.td [AArch64] Add pipeline model for HiSilicon's TSV110 2020-11-07 01:23:00 +03:00
AArch64SchedThunderX.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX2T99.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX3T110.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp [CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize 2020-08-11 12:17:10 +01:00
AArch64SelectionDAGInfo.h [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align 2020-06-30 12:46:26 +00:00
AArch64SpeculationHardening.cpp
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AArch64StackTagging.cpp Use cast<> instead of dyn_cast<> as we dereference the pointer immediately. NFCI. 2020-10-30 14:33:20 +00:00
AArch64StackTaggingPreRA.cpp [MTE] Pin the tagged base pointer to one of the stack slots. 2020-10-15 12:50:16 -07:00
AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp [ARM][AArch64] Adding Neoverse V1 CPU support 2020-11-09 13:15:40 +00:00
AArch64Subtarget.h [AArch64] Enable RAS 1.1 system registers in all AArch64 2020-11-10 12:13:33 +00:00
AArch64SystemOperands.td [AArch64] Enable RAS 1.1 system registers in all AArch64 2020-11-10 12:13:33 +00:00
AArch64TargetMachine.cpp [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
AArch64TargetMachine.h Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile 2020-03-20 21:57:34 -07:00
AArch64TargetObjectFile.h [llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation 2020-06-10 11:34:16 -07:00
AArch64TargetTransformInfo.cpp Reland "[TTI] Add VecPred argument to getCmpSelInstrCost." 2020-11-02 15:39:29 +00:00
AArch64TargetTransformInfo.h [SelectionDAG] Add legalizations for VECREDUCE_SEQ_FMUL 2020-11-04 14:20:31 -06:00
CMakeLists.txt [AArch64][GlobalISel] Introduce a new post-isel optimization pass. 2020-10-23 10:18:36 -07:00
LLVMBuild.txt
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SVEInstrFormats.td [AArch64][SVE] Fix umin/umax lowering to handle out of range imm. 2020-10-23 09:42:56 -07:00
SVEIntrinsicOpts.cpp [SVE] Fix bug in SVEIntrinsicOpts::optimizePTest 2020-08-14 07:57:21 +01:00