forked from OSchip/llvm-project
184 lines
6.3 KiB
C++
184 lines
6.3 KiB
C++
//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Mips specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsELFStreamer.h"
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#include "MipsMCAsmInfo.h"
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#include "MipsMCNaCl.h"
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#include "MipsMCTargetDesc.h"
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#include "MipsTargetStreamer.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCCodeGenInfo.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_MC_DESC
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#include "MipsGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "MipsGenSubtargetInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "MipsGenRegisterInfo.inc"
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/// Select the Mips CPU for the given triple and cpu name.
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/// FIXME: Merge with the copy in MipsSubtarget.cpp
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StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
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if (CPU.empty() || CPU == "generic") {
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if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
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CPU = "mips32";
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else
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CPU = "mips64";
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}
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return CPU;
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}
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static MCInstrInfo *createMipsMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitMipsMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitMipsMCRegisterInfo(X, Mips::RA);
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return X;
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}
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static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
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StringRef CPU, StringRef FS) {
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CPU = MIPS_MC::selectMipsCPU(TT, CPU);
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return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
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}
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static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT) {
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MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
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unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
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MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCCodeGenInfo *createMipsMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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if (CM == CodeModel::JITDefault)
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RM = Reloc::Static;
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else if (RM == Reloc::Default)
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RM = Reloc::PIC_;
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X->initMCCodeGenInfo(RM, CM, OL);
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return X;
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}
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static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new MipsInstPrinter(MAI, MII, MRI);
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}
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static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
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MCAsmBackend &MAB, raw_pwrite_stream &OS,
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MCCodeEmitter *Emitter, bool RelaxAll) {
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MCStreamer *S;
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if (!T.isOSNaCl())
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S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
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else
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S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
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return S;
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}
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static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint,
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bool isVerboseAsm) {
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return new MipsTargetAsmStreamer(S, OS);
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}
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static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
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return new MipsTargetStreamer(S);
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}
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static MCTargetStreamer *
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createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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return new MipsTargetELFStreamer(S, STI);
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}
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extern "C" void LLVMInitializeMipsTargetMC() {
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for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target,
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&TheMips64elTarget}) {
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// Register the MC asm info.
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RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(*T, createMipsMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
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// Register the elf streamer.
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TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
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// Register the asm target streamer.
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TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
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TargetRegistry::RegisterNullTargetStreamer(*T,
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createMipsNullTargetStreamer);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
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TargetRegistry::RegisterObjectTargetStreamer(
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*T, createMipsObjectTargetStreamer);
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}
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// Register the MC Code Emitter
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for (Target *T : {&TheMipsTarget, &TheMips64Target})
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TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
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for (Target *T : {&TheMipselTarget, &TheMips64elTarget})
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TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
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// Register the asm backend.
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TargetRegistry::RegisterMCAsmBackend(TheMipsTarget,
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createMipsAsmBackendEB32);
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TargetRegistry::RegisterMCAsmBackend(TheMipselTarget,
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createMipsAsmBackendEL32);
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TargetRegistry::RegisterMCAsmBackend(TheMips64Target,
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createMipsAsmBackendEB64);
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TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget,
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createMipsAsmBackendEL64);
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}
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