forked from OSchip/llvm-project
106 lines
3.8 KiB
C++
106 lines
3.8 KiB
C++
//===--- WebAssemblyOptimizeLiveIntervals.cpp - LiveInterval processing ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief Optimize LiveIntervals for use in a post-RA context.
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//
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/// LiveIntervals normally runs before register allocation when the code is
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/// only recently lowered out of SSA form, so it's uncommon for registers to
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/// have multiple defs, and then they do, the defs are usually closely related.
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/// Later, after coalescing, tail duplication, and other optimizations, it's
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/// more common to see registers with multiple unrelated defs. This pass
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/// updates LiveIntervalAnalysis to distribute the value numbers across separate
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/// LiveIntervals.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-optimize-live-intervals"
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namespace {
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class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass {
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StringRef getPassName() const override {
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return "WebAssembly Optimize Live Intervals";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(LiveVariablesID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyOptimizeLiveIntervals() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyOptimizeLiveIntervals::ID = 0;
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FunctionPass *llvm::createWebAssemblyOptimizeLiveIntervals() {
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return new WebAssemblyOptimizeLiveIntervals();
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}
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bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n"
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"********** Function: "
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<< MF.getName() << '\n');
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MachineRegisterInfo &MRI = MF.getRegInfo();
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LiveIntervals &LIS = getAnalysis<LiveIntervals>();
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// We don't preserve SSA form.
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MRI.leaveSSA();
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assert(MRI.tracksLiveness() &&
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"OptimizeLiveIntervals expects liveness");
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// Split multiple-VN LiveIntervals into multiple LiveIntervals.
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SmallVector<LiveInterval*, 4> SplitLIs;
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for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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if (MRI.reg_nodbg_empty(Reg))
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continue;
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LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
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SplitLIs.clear();
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}
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// In PrepareForLiveIntervals, we conservatively inserted IMPLICIT_DEF
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// instructions to satisfy LiveIntervals' requirement that all uses be
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// dominated by defs. Now that LiveIntervals has computed which of these
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// defs are actually needed and which are dead, remove the dead ones.
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for (auto MII = MF.begin()->begin(), MIE = MF.begin()->end(); MII != MIE; ) {
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MachineInstr *MI = &*MII++;
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if (MI->isImplicitDef() && MI->getOperand(0).isDead()) {
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LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
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LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
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LIS.RemoveMachineInstrFromMaps(*MI);
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MI->eraseFromParent();
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}
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}
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return false;
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}
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