forked from OSchip/llvm-project
112 lines
3.6 KiB
C++
112 lines
3.6 KiB
C++
//===-- WebAssemblyArgumentMove.cpp - Argument instruction moving ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file moves ARGUMENT instructions after ScheduleDAG scheduling.
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///
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/// Arguments are really live-in registers, however, since we use virtual
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/// registers and LLVM doesn't support live-in virtual registers, we're
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/// currently making do with ARGUMENT instructions which are placed at the top
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/// of the entry block. The trick is to get them to *stay* at the top of the
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/// entry block.
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///
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/// The ARGUMENTS physical register keeps these instructions pinned in place
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/// during liveness-aware CodeGen passes, however one thing which does not
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/// respect this is the ScheduleDAG scheduler. This pass is therefore run
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/// immediately after that.
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///
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/// This is all hopefully a temporary solution until we find a better solution
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/// for describing the live-in nature of arguments.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-argument-move"
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namespace {
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class WebAssemblyArgumentMove final : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyArgumentMove() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return "WebAssembly Argument Move"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // end anonymous namespace
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char WebAssemblyArgumentMove::ID = 0;
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FunctionPass *llvm::createWebAssemblyArgumentMove() {
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return new WebAssemblyArgumentMove();
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}
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/// Test whether the given instruction is an ARGUMENT.
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static bool IsArgument(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case WebAssembly::ARGUMENT_I32:
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case WebAssembly::ARGUMENT_I64:
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case WebAssembly::ARGUMENT_F32:
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case WebAssembly::ARGUMENT_F64:
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case WebAssembly::ARGUMENT_v16i8:
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case WebAssembly::ARGUMENT_v8i16:
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case WebAssembly::ARGUMENT_v4i32:
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case WebAssembly::ARGUMENT_v4f32:
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return true;
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default:
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return false;
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}
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}
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bool WebAssemblyArgumentMove::runOnMachineFunction(MachineFunction &MF) {
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DEBUG({
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dbgs() << "********** Argument Move **********\n"
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<< "********** Function: " << MF.getName() << '\n';
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});
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bool Changed = false;
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MachineBasicBlock &EntryMBB = MF.front();
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MachineBasicBlock::iterator InsertPt = EntryMBB.end();
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// Look for the first NonArg instruction.
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for (MachineInstr &MI : EntryMBB) {
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if (!IsArgument(MI)) {
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InsertPt = MI;
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break;
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}
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}
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// Now move any argument instructions later in the block
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// to before our first NonArg instruction.
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for (MachineInstr &MI : llvm::make_range(InsertPt, EntryMBB.end())) {
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if (IsArgument(MI)) {
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EntryMBB.insert(InsertPt, MI.removeFromParent());
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Changed = true;
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}
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}
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return Changed;
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}
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