forked from OSchip/llvm-project
53 lines
1.9 KiB
LLVM
53 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip
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; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s -check-prefix=X32
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; Control Flow Guard is currently only available on Windows
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; Test that Control Flow Guard checks are correctly added for x86 vector calls.
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define void @func_cf_vector_x86(void (%struct.HVA)* %0, %struct.HVA* %1) #0 {
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; X32-LABEL: func_cf_vector_x86:
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; X32: # %bb.0: # %entry
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; X32-NEXT: pushl %ebp
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: andl $-16, %esp
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; X32-NEXT: subl $48, %esp
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; X32-NEXT: movl 8(%ebp), %ecx
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; X32-NEXT: movl 12(%ebp), %eax
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; X32-NEXT: movups (%eax), %xmm0
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; X32-NEXT: movups 16(%eax), %xmm1
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; X32-NEXT: movaps %xmm0, (%esp)
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; X32-NEXT: movaps %xmm1, 16(%esp)
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; X32-NEXT: movsd (%esp), %xmm4
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; X32-NEXT: movsd 8(%esp), %xmm5
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; X32-NEXT: movsd 16(%esp), %xmm6
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; X32-NEXT: movsd 24(%esp), %xmm7
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; X32-NEXT: calll *___guard_check_icall_fptr
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; X32-NEXT: movaps %xmm4, %xmm0
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; X32-NEXT: movaps %xmm5, %xmm1
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; X32-NEXT: movaps %xmm6, %xmm2
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; X32-NEXT: movaps %xmm7, %xmm3
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; X32-NEXT: calll *%ecx
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; X32-NEXT: movl %ebp, %esp
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; X32-NEXT: popl %ebp
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; X32-NEXT: retl
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entry:
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%2 = alloca %struct.HVA, align 8
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%3 = bitcast %struct.HVA* %2 to i8*
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%4 = bitcast %struct.HVA* %1 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %3, i8* align 8 %4, i32 32, i1 false)
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%5 = load %struct.HVA, %struct.HVA* %2, align 8
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call x86_vectorcallcc void %0(%struct.HVA inreg %5)
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ret void
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}
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attributes #0 = { "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" }
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%struct.HVA = type { double, double, double, double }
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1 immarg) #1
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attributes #1 = { argmemonly nounwind willreturn }
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!llvm.module.flags = !{!0}
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!0 = !{i32 2, !"cfguard", i32 2}
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