forked from OSchip/llvm-project
114 lines
4.2 KiB
C++
114 lines
4.2 KiB
C++
//=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// When the compiler is invoked with no small data, for instance, with the -G0
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// command line option, then all CONST* opcodes should be broken down into
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// appropriate LO and HI instructions. This splitting is done by this pass.
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// The only reason this is not done in the DAG lowering itself is that there
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// is no simple way of getting the register allocator to allot the same hard
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// register to the result of LO and HI instructions. This pass is always
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// scheduled after register allocation.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "HexagonTargetObjectFile.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "xfer"
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namespace llvm {
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FunctionPass *createHexagonSplitConst32AndConst64();
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void initializeHexagonSplitConst32AndConst64Pass(PassRegistry&);
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}
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namespace {
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class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
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public:
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static char ID;
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HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {
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PassRegistry &R = *PassRegistry::getPassRegistry();
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initializeHexagonSplitConst32AndConst64Pass(R);
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}
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StringRef getPassName() const override {
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return "Hexagon Split Const32s and Const64s";
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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};
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}
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char HexagonSplitConst32AndConst64::ID = 0;
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INITIALIZE_PASS(HexagonSplitConst32AndConst64, "split-const-for-sdata",
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"Hexagon Split Const32s and Const64s", false, false)
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bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
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auto &HST = Fn.getSubtarget<HexagonSubtarget>();
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auto &HTM = static_cast<const HexagonTargetMachine&>(Fn.getTarget());
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auto &TLOF = *HTM.getObjFileLowering();
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if (HST.useSmallData() && TLOF.isSmallDataEnabled(HTM))
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return false;
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const TargetInstrInfo *TII = HST.getInstrInfo();
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const TargetRegisterInfo *TRI = HST.getRegisterInfo();
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// Loop over all of the basic blocks
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for (MachineBasicBlock &B : Fn) {
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for (auto I = B.begin(), E = B.end(); I != E; ) {
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MachineInstr &MI = *I;
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++I;
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unsigned Opc = MI.getOpcode();
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if (Opc == Hexagon::CONST32) {
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unsigned DestReg = MI.getOperand(0).getReg();
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uint64_t ImmValue = MI.getOperand(1).getImm();
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const DebugLoc &DL = MI.getDebugLoc();
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BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg)
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.addImm(ImmValue);
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B.erase(&MI);
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} else if (Opc == Hexagon::CONST64) {
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unsigned DestReg = MI.getOperand(0).getReg();
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int64_t ImmValue = MI.getOperand(1).getImm();
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const DebugLoc &DL = MI.getDebugLoc();
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unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
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unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
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int32_t LowWord = (ImmValue & 0xFFFFFFFF);
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int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
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BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
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.addImm(LowWord);
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BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
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.addImm(HighWord);
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B.erase(&MI);
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}
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}
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}
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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FunctionPass *llvm::createHexagonSplitConst32AndConst64() {
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return new HexagonSplitConst32AndConst64();
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}
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