forked from OSchip/llvm-project
33 lines
1.6 KiB
TableGen
33 lines
1.6 KiB
TableGen
//===--- HexagonOperands.td -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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def f32ImmOperand : AsmOperandClass { let Name = "f32Imm"; }
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def f32Imm : Operand<f32> { let ParserMatchClass = f32ImmOperand; }
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def f64ImmOperand : AsmOperandClass { let Name = "f64Imm"; }
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def f64Imm : Operand<f64> { let ParserMatchClass = f64ImmOperand; }
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def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>;
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def s9_0ImmOperand : AsmOperandClass { let Name = "s9_0Imm"; }
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def s9_0Imm : Operand<i32> { let ParserMatchClass = s9_0ImmOperand; }
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def s27_2ImmOperand : AsmOperandClass { let Name = "s27_2Imm"; let RenderMethod = "addSignedImmOperands"; }
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def s27_2Imm : Operand<i32> { let ParserMatchClass = s27_2ImmOperand; }
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def r32_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isInt<32>(v);
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}]>;
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def u9_0ImmPred : PatLeaf<(i32 imm), [{
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int64_t v = (int64_t)N->getSExtValue();
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return isUInt<9>(v);
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}]>;
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def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; let RenderMethod = "addImmOperands"; }
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def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }
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def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; }
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def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; }
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def bblabel : Operand<i32>;
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def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">;
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