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dpp_vi.txt
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[AMDGPU] Disassembler: support for DPP
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2016-03-31 14:15:04 +00:00 |
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ds_vi.txt
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[AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
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2016-10-21 14:49:22 +00:00 |
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flat_vi.txt
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[AMDGPU] add VI disassembler tests. NFC.
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2016-03-17 17:56:33 +00:00 |
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lit.local.cfg
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…
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mov.txt
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…
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mubuf_vi.txt
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[AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.
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2016-10-07 15:53:16 +00:00 |
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nop.txt
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…
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sdwa_vi.txt
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[AMDGPU] Add f16 support (VI+)
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2016-11-13 07:01:11 +00:00 |
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smem_vi.txt
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[AMDGPU] Disassembler: fix s_buffer_store_dword instructions
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2016-12-05 09:58:51 +00:00 |
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smrd_vi.txt
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[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.
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2016-10-31 16:07:39 +00:00 |
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sop1_vi.txt
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[AMDGPU] add VI disassembler tests. NFC.
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2016-03-17 17:56:33 +00:00 |
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sop2_vi.txt
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[AMDGPU] add VI disassembler tests. NFC.
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2016-03-17 17:56:33 +00:00 |
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sopc_vi.txt
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[AMDGPU] add VI disassembler tests. NFC.
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2016-03-17 17:56:33 +00:00 |
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sopk_vi.txt
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[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.
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2016-04-27 15:17:03 +00:00 |
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sopp_vi.txt
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[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.
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2016-05-06 17:48:48 +00:00 |
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trap_vi.txt
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[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.
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2016-05-24 12:05:16 +00:00 |
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vintrp.txt
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AMDGPU: Fix vintrp disassembly
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2016-12-10 00:29:55 +00:00 |
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vop1.txt
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…
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vop1_vi.txt
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[AMDGPU] Add some VI disassembler tests missing from previous autogeneration due to different filecheck prefix. NFC.
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2016-04-08 05:42:20 +00:00 |
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vop2_vi.txt
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[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC.
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2016-06-06 15:23:43 +00:00 |
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vop3_vi.txt
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[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC.
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2016-06-06 15:23:43 +00:00 |
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vopc_vi.txt
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[AMDGPU] add VI disassembler tests. NFC.
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2016-03-17 17:56:33 +00:00 |
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