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AArch64
[AArch64][GlobalISel]: Fix a crash in GlobalIsel in dealing with 16bit uadd.with.overflow.
2019-12-17 16:05:00 -08:00
AMDGPU
[AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtr
2019-12-17 18:54:27 +00:00
ARC
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ARM
[FPEnv] Remove unnecessary rounding mode argument for constrained intrinsics
2019-12-17 21:10:36 +01:00
AVR
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BPF
[BPF] put not-section-attribute externs into BTF ".extern" data section
2019-12-10 11:45:17 -08:00
Generic
[CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2
2019-11-02 23:59:12 -04:00
Hexagon
[ModuloSchedule] Fix a bug in experimental expander
2019-11-23 16:01:47 -08:00
Inputs
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Lanai
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MIR
[llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.
2019-12-16 18:25:04 -05:00
MSP430
[TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4)
2019-11-13 09:23:08 +01:00
Mips
[Mips] Add support for min/max/umin/umax atomics
2019-12-12 11:32:37 +01:00
NVPTX
[NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics
2019-10-28 13:55:30 -07:00
PowerPC
[PowerPC] Add missing legalization for vector BSWAP
2019-12-17 19:07:34 -06:00
RISCV
[RISCV] Add subtargets initialized with target feature
2019-12-17 09:34:01 -08:00
SPARC
Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that
2019-12-03 11:21:52 +01:00
SystemZ
[FPEnv] Remove unnecessary rounding mode argument for constrained intrinsics
2019-12-17 21:10:36 +01:00
Thumb
Revert "ARM-Darwin: keep the frame register reserved even if not updated."
2019-12-06 10:59:26 -08:00
Thumb2
[ARM][MVE][Intrinsics] All vqdmulhq/vqrdmulhq tests should be for signed numbers.
2019-12-13 17:29:59 +00:00
WebAssembly
[WebAssembly] Implement SIMD {i8x16,i16x8}.avgr_u instructions
2019-12-17 15:05:50 -08:00
WinCFGuard
[WinCFG] Handle constant casts carefully in .gfids emission
2019-11-01 13:32:03 -07:00
WinEH
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X86
[X86] Add calculation for elements in structures in getting uniform base for the Gather/Scatter intrinsic.
2019-12-18 12:24:58 +08:00
XCore
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8cc0b58673