forked from OSchip/llvm-project
491 lines
14 KiB
LLVM
491 lines
14 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; CHECK-LABEL: test:
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; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: property_access1:
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; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: property_access2:
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; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: property_access3:
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; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: anyreg_test1:
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; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: anyreg_test2:
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; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: patchpoint_spilldef:
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; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}
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; CHECK-LABEL: patchpoint_spillargs:
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; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
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; Stackmap Header: no constants - 6 callsites
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; CHECK-LABEL: .section .llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; Header
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; Num Functions
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; CHECK-NEXT: .long 8
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; Num LargeConstants
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; CHECK-NEXT: .long 0
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; Num Callsites
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; CHECK-NEXT: .long 8
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; Functions and stack size
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; CHECK-NEXT: .quad test
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access1
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access2
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access3
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; CHECK-NEXT: .quad 128
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad anyreg_test1
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; CHECK-NEXT: .quad 144
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad anyreg_test2
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; CHECK-NEXT: .quad 144
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad patchpoint_spilldef
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; CHECK-NEXT: .quad 256
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad patchpoint_spillargs
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; CHECK-NEXT: .quad 288
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; CHECK-NEXT: .quad 1
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; test
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; CHECK: .long .L{{.*}}-.L[[test_BEGIN]]
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; CHECK-NEXT: .short 0
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; 3 locations
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; CHECK-NEXT: .short 3
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; Loc 0: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 2: Constant 3
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 3
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define i64 @test() nounwind ssp uwtable {
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entry:
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call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, i8* null, i32 2, i32 1, i32 2, i64 3)
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ret i64 0
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}
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; property access 1 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK: .long .L{{.*}}-.L[[property_access1_BEGIN]]
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, i8* %f, i32 1, i8* %obj)
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ret i64 %ret
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}
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; property access 2 - %obj is an anyreg call argument and should therefore be in a register
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; CHECK: .long .L{{.*}}-.L[[property_access2_BEGIN]]
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @property_access2() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, i8* %f, i32 1, i64* %obj)
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ret i64 %ret
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}
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; property access 3 - %obj is a frame index
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; CHECK: .long .L{{.*}}-.L[[property_access3_BEGIN]]
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; CHECK-NEXT: .short 0
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; 2 locations
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; CHECK-NEXT: .short 2
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Direct FP - 8
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 31
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 112
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define i64 @property_access3() nounwind ssp uwtable {
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entry:
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%obj = alloca i64, align 8
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, i8* %f, i32 0, i64* %obj)
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ret i64 %ret
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}
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; anyreg_test1
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; CHECK: .long .L{{.*}}-.L[[anyreg_test1_BEGIN]]
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; CHECK-NEXT: .short 0
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; 14 locations
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; CHECK-NEXT: .short 14
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 12: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 13: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
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ret i64 %ret
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}
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; anyreg_test2
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; CHECK: .long .L{{.*}}-.L[[anyreg_test2_BEGIN]]
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; CHECK-NEXT: .short 0
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; 14 locations
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; CHECK-NEXT: .short 14
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; Loc 0: Register <-- this is the return register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 2: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 3: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 4: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 5: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 6: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 7: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 8: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 9: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 10: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 11: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 12: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 13: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
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entry:
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%f = inttoptr i64 281474417671919 to i8*
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%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
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ret i64 %ret
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}
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; Test spilling the return value of an anyregcc call.
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;
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; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
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;
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; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 3
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; Loc 0: Register (some register that will be spilled to the stack)
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
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tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
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},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
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ret i64 %result
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}
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; Test spilling the arguments of an anyregcc call.
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;
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; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
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;
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; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 5
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; Loc 0: Return a register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Arg0 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 2: Arg1 in a Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 3: Arg2 spilled to FP -96
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 31
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 128
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|
; Loc 4: Arg3 spilled to FP - 88
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|
; CHECK-NEXT: .byte 3
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|
; CHECK-NEXT: .byte 0
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|
; CHECK-NEXT: .short 8
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; CHECK-NEXT: .short 31
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 136
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define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
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},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
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%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
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ret i64 %result
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}
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|
|
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declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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