forked from OSchip/llvm-project
240 lines
5.9 KiB
LLVM
240 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P9
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-P8
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define signext i64 @maddld64(i64 signext %a, i64 signext %b) {
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; CHECK-LABEL: maddld64:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P8-NEXT: mulld 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i64 %b, %a
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%add = add i64 %mul, %a
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ret i64 %add
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}
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define signext i32 @maddld32(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: maddld32:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P9-NEXT: extsw 3, 3
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-P8-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, %a
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ret i32 %add
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}
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define signext i16 @maddld16(i16 signext %a, i16 signext %b, i16 signext %c) {
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; CHECK-LABEL: maddld16:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 5
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; CHECK-P9-NEXT: extsh 3, 3
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; CHECK-P8-NEXT: mullw 3, 4, 3
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; CHECK-P8-NEXT: add 3, 3, 5
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; CHECK-P8-NEXT: extsh 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i16 %b, %a
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%add = add i16 %mul, %c
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ret i16 %add
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}
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define zeroext i32 @maddld32zeroext(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: maddld32zeroext:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, %a
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ret i32 %add
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}
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define signext i32 @maddld32nsw(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: maddld32nsw:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul nsw i32 %b, %a
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: maddld 3, 4, 3, 3
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; CHECK-P8-NEXT: mullw 4, 4, 3
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; CHECK-P8-NEXT: add 3, 4, 3
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, %a
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%add = add nuw i32 %mul, %a
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ret i32 %add
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}
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define signext i64 @maddld64_imm(i64 signext %a, i64 signext %b) {
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; CHECK-LABEL: maddld64_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 4, 4, 13
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; CHECK-NEXT: add 3, 4, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i64 %b, 13
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%add = add i64 %mul, %a
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ret i64 %add
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}
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define signext i32 @maddld32_imm(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: maddld32_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, 13
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ret i32 %add
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}
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define signext i16 @maddld16_imm(i16 signext %a, i16 signext %b, i16 signext %c) {
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; CHECK-LABEL: maddld16_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 3, 4, 13
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; CHECK-NEXT: add 3, 3, 5
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; CHECK-NEXT: extsh 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul i16 %b, 13
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%add = add i16 %mul, %c
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ret i16 %add
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}
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define zeroext i32 @maddld32zeroext_imm(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: maddld32zeroext_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul i32 %b, %a
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%add = add i32 %mul, 13
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ret i32 %add
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}
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define signext i32 @maddld32nsw_imm(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: maddld32nsw_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 4, 4, 13
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; CHECK-NEXT: add 3, 4, 3
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; CHECK-NEXT: extsw 3, 3
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; CHECK-NEXT: blr
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entry:
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%mul = mul nsw i32 %b, 13
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_imm(i32 zeroext %a, i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mullw 3, 4, 3
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, %a
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%add = add nuw i32 %mul, 13
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_imm_imm(i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_imm_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: mulli 3, 3, 18
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, 18
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%add = add nuw i32 %mul, 13
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_bigimm_imm(i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_bigimm_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NOT: maddld
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; CHECK-NEXT: lis 4, 26127
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; CHECK-NEXT: ori 4, 4, 63251
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; CHECK-NEXT: mullw 3, 3, 4
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; CHECK-NEXT: addi 3, 3, 13
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, 1712322323
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%add = add nuw i32 %mul, 13
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ret i32 %add
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}
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define zeroext i32 @maddld32nuw_bigimm_bigimm(i32 zeroext %b) {
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; CHECK-LABEL: maddld32nuw_bigimm_bigimm:
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; CHECK: # %bb.0: # %entry
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; CHECK-P9-NEXT: lis 4, -865
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; CHECK-P9-NEXT: lis 5, 26127
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; CHECK-P9-NEXT: ori 4, 4, 42779
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; CHECK-P9-NEXT: ori 5, 5, 63251
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; CHECK-P9-NEXT: maddld 3, 3, 5, 4
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; CHECK-P8-NEXT: lis 4, 26127
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; CHECK-P8-NEXT: ori 4, 4, 63251
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; CHECK-P8-NEXT: mullw 3, 3, 4
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; CHECK-P8-NEXT: addi 3, 3, -22757
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; CHECK-P8-NEXT: addis 3, 3, -864
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%mul = mul nuw i32 %b, 1712322323
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%add = add nuw i32 %mul, 17123223323
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ret i32 %add
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}
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