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llvm-project/mlir/lib/Conversion
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Mehdi Amini 973ddb7d6e Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 
In particular for Graph Regions, the terminator needs is just a
historical artifact of the generalization of MLIR from CFG region.
Operations like Module don't need a terminator, and before Module
migrated to be an operation with region there wasn't any needed.

To validate the feature, the ModuleOp is migrated to use this trait and
the ModuleTerminator operation is deleted.

This patch is likely to break clients, if you're in this case:

- you may iterate on a ModuleOp with `getBody()->without_terminator()`,
  the solution is simple: just remove the ->without_terminator!
- you created a builder with `Builder::atBlockTerminator(module_body)`,
  just use `Builder::atBlockEnd(module_body)` instead.
- you were handling ModuleTerminator: it isn't needed anymore.
- for generic code, a `Block::mayNotHaveTerminator()` may be used.

Differential Revision: https://reviews.llvm.org/D98468
 		2021-03-25 03:59:03 +00:00
..
AffineToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
ArmSVEToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
AsyncToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
ComplexToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
GPUCommon Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
GPUToNVVM [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
GPUToROCDL [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
GPUToSPIRV [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
GPUToVulkan Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToSPIRV Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToStandard Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
OpenMPToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
PDLToPDLInterp [mlir][pdl] Cast the OperationPosition to Position to fix MSVC miscompile 2021-03-16 16:11:14 -07:00
SCFToGPU [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SCFToOpenMP Rename FrozenRewritePatternList -> FrozenRewritePatternSet; NFC. 2021-03-22 17:40:45 -07:00
SCFToSPIRV [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SCFToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SPIRVToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
ShapeToStandard Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
StandardToLLVM [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
StandardToSPIRV [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
TosaToLinalg [mlir][tosa] Add tosa.bitwise_not lowering to constant and xor 2021-03-24 17:27:27 -07:00
TosaToSCF [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
TosaToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
VectorToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
VectorToROCDL [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
VectorToSCF [mlir][NFC] Replace `getMemorySpaceAsInt` with `getMemorySpace` where possible 2021-03-24 13:23:59 +03:00
VectorToSPIRV Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
CMakeLists.txt [mlir] squash LLVM_AVX512 dialect into AVX512 2021-03-10 13:07:26 +01:00
PassDetail.h [mlir][amx] Add Intel AMX dialect (architectural-specific vector dialect) 2021-03-15 17:59:05 -07:00