llvm-project/llvm/test/CodeGen/MIR/PowerPC
Kai Luo fec7da8285 [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register
Summary:
When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check
if `extsw`'s second operand is a virtual register, otherwise we might
get miscompile.

Differential Revision: https://reviews.llvm.org/D65315

llvm-svn: 367645
2019-08-02 03:14:17 +00:00
..
ifcvt-diamond-ret.mir
lit.local.cfg
peephole-miscompile-extswsli.mir [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register 2019-08-02 03:14:17 +00:00
prolog_vec_spills.mir
unordered-implicit-registers.mir