llvm-project

History

Matt Arsenault ff07631b48 AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization llvm-svn: 370089		2019-08-27 18:18:38 +00:00
..
AArch64	GlobalISel: Add more verifier checks for G_SHUFFLE_VECTOR	2019-08-13 15:52:21 +00:00
AMDGPU	AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization	2019-08-27 18:18:38 +00:00
ARM	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Generic	Rename ExpandISelPseudo->FinalizeISel, delay register reservation	2019-06-19 00:25:39 +00:00
Hexagon	[DebugInfo] Allow bundled calls in the MIR's call site info	2019-08-19 12:41:22 +00:00
Mips	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
NVPTX	[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.	2018-01-10 00:56:48 +00:00
PowerPC	[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register	2019-08-02 03:14:17 +00:00
WebAssembly	[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)	2018-05-08 02:02:50 +00:00
X86	[DebugInfo] MCP: collect and update DBG_VALUEs encountered in local block	2019-08-14 12:20:02 +00:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.