forked from OSchip/llvm-project
119 lines
3.7 KiB
YAML
119 lines
3.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: bitreverse_i32_ss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: bitreverse_i32_ss
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[S_BREV_B32_:%[0-9]+]]:sreg_32 = S_BREV_B32 [[COPY]]
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; CHECK: S_ENDPGM 0, implicit [[S_BREV_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = G_BITREVERSE %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: bitreverse_i32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: bitreverse_i32_vv
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = G_BITREVERSE %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: bitreverse_i32_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: bitreverse_i32_vs
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; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec
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; CHECK: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = G_BITREVERSE %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: bitreverse_i64_ss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: bitreverse_i64_ss
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[S_BREV_B64_:%[0-9]+]]:sreg_64 = S_BREV_B64 [[COPY]]
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; CHECK: S_ENDPGM 0, implicit [[S_BREV_B64_]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_BITREVERSE %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: bitreverse_i64_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: bitreverse_i64_vv
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; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
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; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec
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; CHECK: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub1
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; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%2:vgpr(s32), %3:vgpr(s32) = G_UNMERGE_VALUES %0(s64)
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%4:vgpr(s32) = G_BITREVERSE %3
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%5:vgpr(s32) = G_BITREVERSE %2
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%1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32)
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S_ENDPGM 0, implicit %1
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...
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---
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name: bitreverse_i64_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: bitreverse_i64_vs
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
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; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
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; CHECK: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec
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; CHECK: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec
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; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub1
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; CHECK: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0(s64)
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%4:vgpr(s32) = G_BITREVERSE %3
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%5:vgpr(s32) = G_BITREVERSE %2
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%1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32)
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S_ENDPGM 0, implicit %1
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...
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