forked from OSchip/llvm-project
919 lines
54 KiB
C++
919 lines
54 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -disable-O0-optnone -o - | FileCheck %s --check-prefix=CHECK5
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-linux -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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void fn1();
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void fn2();
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void fn3();
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void fn4();
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void fn5();
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void fn6();
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int Arg;
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void gtid_test() {
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#pragma omp parallel
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#pragma omp parallel if (parallel: false)
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gtid_test();
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}
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template <typename T>
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int tmain(T Arg) {
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#pragma omp parallel if (true)
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fn1();
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#pragma omp parallel if (false)
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fn2();
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#pragma omp parallel if (parallel: Arg)
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fn3();
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return 0;
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}
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int main() {
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#pragma omp parallel if (true)
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fn4();
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#pragma omp parallel if (false)
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fn5();
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#pragma omp parallel if (Arg)
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fn6();
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return tmain(Arg);
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}
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#endif
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// CHECK1-LABEL: define {{[^@]+}}@_Z9gtid_testv
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// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
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// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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// CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]]
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// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @_Z9gtid_testv()
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@main
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// CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
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// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
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// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
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// CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4
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// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*))
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// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK1-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
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// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4
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// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
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// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
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// CHECK1: omp_if.then:
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// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
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// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
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// CHECK1: omp_if.else:
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// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
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// CHECK1-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
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// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: br label [[OMP_IF_END]]
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// CHECK1: omp_if.end:
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// CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4
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// CHECK1-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]])
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// CHECK1-NEXT: ret i32 [[CALL]]
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @_Z3fn4v()
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @_Z3fn5v()
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @_Z3fn6v()
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
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// CHECK1-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
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// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
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// CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
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// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
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// CHECK1-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4
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// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*))
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// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
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// CHECK1-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
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// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4
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// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
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// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
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// CHECK1: omp_if.then:
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// CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
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// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
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// CHECK1: omp_if.else:
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// CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
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// CHECK1-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
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// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
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// CHECK1-NEXT: br label [[OMP_IF_END]]
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// CHECK1: omp_if.end:
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// CHECK1-NEXT: ret i32 0
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @_Z3fn1v()
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @_Z3fn2v()
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
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// CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
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// CHECK1-NEXT: entry:
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// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK1-NEXT: call void @_Z3fn3v()
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// CHECK1-NEXT: ret void
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//
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//
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// CHECK2-LABEL: define {{[^@]+}}@_Z9gtid_testv
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// CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
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// CHECK2-NEXT: entry:
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// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
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// CHECK2-NEXT: ret void
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//
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//
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// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
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// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
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// CHECK2-NEXT: entry:
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// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
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// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
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// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
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// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
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// CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
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// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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// CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
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// CHECK2-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]]
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// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
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// CHECK2-NEXT: ret void
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//
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//
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// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
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|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: call void @_Z9gtid_testv()
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@main
|
|
// CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK2-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK2-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK2-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]])
|
|
// CHECK2-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: call void @_Z3fn4v()
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: call void @_Z3fn5v()
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: call void @_Z3fn6v()
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
|
|
// CHECK2-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK2-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK2-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4
|
|
// CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK2: omp_if.then:
|
|
// CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK2-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK2: omp_if.else:
|
|
// CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK2-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK2-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK2: omp_if.end:
|
|
// CHECK2-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: call void @_Z3fn1v()
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: call void @_Z3fn2v()
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK2-NEXT: entry:
|
|
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK2-NEXT: call void @_Z3fn3v()
|
|
// CHECK2-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z9gtid_testv
|
|
// CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @_Z9gtid_testv()
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@main
|
|
// CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK5-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*))
|
|
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK5-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK5-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK5-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]])
|
|
// CHECK5-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @_Z3fn4v()
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @_Z3fn5v()
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @_Z3fn6v()
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
|
|
// CHECK5-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK5-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*))
|
|
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK5-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4
|
|
// CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK5: omp_if.then:
|
|
// CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK5-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK5: omp_if.else:
|
|
// CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK5-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK5-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK5: omp_if.end:
|
|
// CHECK5-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @_Z3fn1v()
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @_Z3fn2v()
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK5-NEXT: entry:
|
|
// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK5-NEXT: call void @_Z3fn3v()
|
|
// CHECK5-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z9gtid_testv
|
|
// CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @_Z9gtid_testv()
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@main
|
|
// CHECK6-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK6-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*))
|
|
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK6-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK6-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]])
|
|
// CHECK6-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @_Z3fn4v()
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @_Z3fn5v()
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @_Z3fn6v()
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
|
|
// CHECK6-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK6-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK6-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*))
|
|
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK6-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4
|
|
// CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK6: omp_if.then:
|
|
// CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK6-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK6: omp_if.else:
|
|
// CHECK6-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK6-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK6-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK6-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK6: omp_if.end:
|
|
// CHECK6-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @_Z3fn1v()
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @_Z3fn2v()
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK6-NEXT: entry:
|
|
// CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK6-NEXT: call void @_Z3fn3v()
|
|
// CHECK6-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z9gtid_testv
|
|
// CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
|
|
// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @.omp_outlined..1(i32* [[TMP2]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]]
|
|
// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @_Z9gtid_testv()
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@main
|
|
// CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK7-NEXT: store i32 0, i32* [[RETVAL]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*))
|
|
// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK7-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK7-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* @Arg, align 4
|
|
// CHECK7-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiEiT_(i32 [[TMP2]])
|
|
// CHECK7-NEXT: ret i32 [[CALL]]
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @_Z3fn4v()
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @_Z3fn5v()
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @_Z3fn6v()
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_
|
|
// CHECK7-SAME: (i32 [[ARG:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTTHREADID_TEMP_1:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR2]], align 4
|
|
// CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
|
|
// CHECK7-NEXT: store i32 [[ARG]], i32* [[ARG_ADDR]], align 4
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..5 to void (i32*, i32*, ...)*))
|
|
// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
|
|
// CHECK7-NEXT: call void @.omp_outlined..6(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
|
|
// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARG_ADDR]], align 4
|
|
// CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
|
|
// CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK7: omp_if.then:
|
|
// CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
|
|
// CHECK7-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK7: omp_if.else:
|
|
// CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_1]], align 4
|
|
// CHECK7-NEXT: call void @.omp_outlined..7(i32* [[DOTTHREADID_TEMP_1]], i32* [[DOTBOUND_ZERO_ADDR2]]) #[[ATTR2]]
|
|
// CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
|
|
// CHECK7-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK7: omp_if.end:
|
|
// CHECK7-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @_Z3fn1v()
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @_Z3fn2v()
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK7-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
|
|
// CHECK7-NEXT: entry:
|
|
// CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
|
|
// CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK7-NEXT: call void @_Z3fn3v()
|
|
// CHECK7-NEXT: ret void
|
|
//
|
|
//
|