forked from OSchip/llvm-project
419 lines
11 KiB
LLVM
419 lines
11 KiB
LLVM
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; Function Attrs: nounwind
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define zeroext i8 @_Z6testcff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i8
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ret i8 %conv
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; CHECK-LABEL: @_Z6testcff
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; CHECK: xscvdpsxws [[CONVREG01:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG01]]
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}
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; Function Attrs: nounwind
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define float @_Z6testfcc(i8 zeroext %arg) {
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to float
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ret float %conv
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; CHECK-LABEL: @_Z6testfcc
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; CHECK: mtvsrwz [[MOVEREG01:[0-9]+]], 3
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; CHECK: xscvuxdsp 1, [[MOVEREG01]]
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}
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; Function Attrs: nounwind
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define zeroext i8 @_Z6testcdd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i8
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ret i8 %conv
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; CHECK-LABEL: @_Z6testcdd
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; CHECK: xscvdpsxws [[CONVREG02:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG02]]
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}
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; Function Attrs: nounwind
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define double @_Z6testdcc(i8 zeroext %arg) {
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z6testdcc
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; CHECK: mtvsrwz [[MOVEREG02:[0-9]+]], 3
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; CHECK: xscvuxddp 1, [[MOVEREG02]]
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}
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; Function Attrs: nounwind
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define zeroext i8 @_Z7testucff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i8
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ret i8 %conv
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; CHECK-LABEL: @_Z7testucff
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; CHECK: xscvdpsxws [[CONVREG03:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG03]]
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}
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; Function Attrs: nounwind
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define float @_Z7testfuch(i8 zeroext %arg) {
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to float
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ret float %conv
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; CHECK-LABEL: @_Z7testfuch
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; CHECK: mtvsrwz [[MOVEREG03:[0-9]+]], 3
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; CHECK: xscvuxdsp 1, [[MOVEREG03]]
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}
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; Function Attrs: nounwind
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define zeroext i8 @_Z7testucdd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i8
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ret i8 %conv
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; CHECK-LABEL: @_Z7testucdd
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; CHECK: xscvdpsxws [[CONVREG04:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG04]]
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}
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; Function Attrs: nounwind
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define double @_Z7testduch(i8 zeroext %arg) {
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entry:
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%arg.addr = alloca i8, align 1
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store i8 %arg, i8* %arg.addr, align 1
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%0 = load i8, i8* %arg.addr, align 1
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%conv = uitofp i8 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z7testduch
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; CHECK: mtvsrwz [[MOVEREG04:[0-9]+]], 3
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; CHECK: xscvuxddp 1, [[MOVEREG04]]
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}
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; Function Attrs: nounwind
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define signext i16 @_Z6testsff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptosi float %0 to i16
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ret i16 %conv
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; CHECK-LABEL: @_Z6testsff
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; CHECK: xscvdpsxws [[CONVREG05:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG05]]
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}
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; Function Attrs: nounwind
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define float @_Z6testfss(i16 signext %arg) {
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = sitofp i16 %0 to float
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ret float %conv
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; CHECK-LABEL: @_Z6testfss
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; CHECK: mtvsrwa [[MOVEREG05:[0-9]+]], 3
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; CHECK: xscvsxdsp 1, [[MOVEREG05]]
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}
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; Function Attrs: nounwind
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define signext i16 @_Z6testsdd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptosi double %0 to i16
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ret i16 %conv
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; CHECK-LABEL: @_Z6testsdd
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; CHECK: xscvdpsxws [[CONVREG06:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG06]]
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}
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; Function Attrs: nounwind
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define double @_Z6testdss(i16 signext %arg) {
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = sitofp i16 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z6testdss
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; CHECK: mtvsrwa [[MOVEREG06:[0-9]+]], 3
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; CHECK: xscvsxddp 1, [[MOVEREG06]]
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}
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; Function Attrs: nounwind
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define zeroext i16 @_Z7testusff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i16
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ret i16 %conv
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; CHECK-LABEL: @_Z7testusff
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; CHECK: xscvdpsxws [[CONVREG07:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG07]]
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}
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; Function Attrs: nounwind
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define float @_Z7testfust(i16 zeroext %arg) {
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = uitofp i16 %0 to float
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ret float %conv
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; CHECK-LABEL: @_Z7testfust
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; CHECK: mtvsrwz [[MOVEREG07:[0-9]+]], 3
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; CHECK: xscvuxdsp 1, [[MOVEREG07]]
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}
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; Function Attrs: nounwind
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define zeroext i16 @_Z7testusdd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i16
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ret i16 %conv
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; CHECK-LABEL: @_Z7testusdd
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; CHECK: xscvdpsxws [[CONVREG08:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG08]]
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}
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; Function Attrs: nounwind
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define double @_Z7testdust(i16 zeroext %arg) {
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entry:
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%arg.addr = alloca i16, align 2
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store i16 %arg, i16* %arg.addr, align 2
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%0 = load i16, i16* %arg.addr, align 2
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%conv = uitofp i16 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z7testdust
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; CHECK: mtvsrwz [[MOVEREG08:[0-9]+]], 3
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; CHECK: xscvuxddp 1, [[MOVEREG08]]
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}
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; Function Attrs: nounwind
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define signext i32 @_Z6testiff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptosi float %0 to i32
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ret i32 %conv
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; CHECK-LABEL: @_Z6testiff
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; CHECK: xscvdpsxws [[CONVREG09:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG09]]
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}
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; Function Attrs: nounwind
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define float @_Z6testfii(i32 signext %arg) {
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = sitofp i32 %0 to float
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ret float %conv
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; CHECK-LABEL: @_Z6testfii
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; CHECK: mtvsrwa [[MOVEREG09:[0-9]+]], 3
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; CHECK: xscvsxdsp 1, [[MOVEREG09]]
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}
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; Function Attrs: nounwind
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define signext i32 @_Z6testidd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptosi double %0 to i32
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ret i32 %conv
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; CHECK-LABEL: @_Z6testidd
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; CHECK: xscvdpsxws [[CONVREG10:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG10]]
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}
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; Function Attrs: nounwind
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define double @_Z6testdii(i32 signext %arg) {
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = sitofp i32 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z6testdii
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; CHECK: mtvsrwa [[MOVEREG10:[0-9]+]], 3
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; CHECK: xscvsxddp 1, [[MOVEREG10]]
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}
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; Function Attrs: nounwind
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define zeroext i32 @_Z7testuiff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i32
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ret i32 %conv
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; CHECK-LABEL: @_Z7testuiff
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; CHECK: xscvdpuxws [[CONVREG11:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG11]]
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}
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; Function Attrs: nounwind
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define float @_Z7testfuij(i32 zeroext %arg) {
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = uitofp i32 %0 to float
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ret float %conv
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; CHECK-LABEL: @_Z7testfuij
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; CHECK: mtvsrwz [[MOVEREG11:[0-9]+]], 3
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; CHECK: xscvuxdsp 1, [[MOVEREG11]]
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}
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; Function Attrs: nounwind
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define zeroext i32 @_Z7testuidd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i32
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ret i32 %conv
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; CHECK-LABEL: @_Z7testuidd
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; CHECK: xscvdpuxws [[CONVREG12:[0-9]+]], 1
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; CHECK: mfvsrwz 3, [[CONVREG12]]
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}
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; Function Attrs: nounwind
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define double @_Z7testduij(i32 zeroext %arg) {
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entry:
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%arg.addr = alloca i32, align 4
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store i32 %arg, i32* %arg.addr, align 4
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%0 = load i32, i32* %arg.addr, align 4
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%conv = uitofp i32 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z7testduij
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; CHECK: mtvsrwz [[MOVEREG12:[0-9]+]], 3
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; CHECK: xscvuxddp 1, [[MOVEREG12]]
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}
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; Function Attrs: nounwind
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define i64 @_Z7testllff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptosi float %0 to i64
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ret i64 %conv
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; CHECK-LABEL: @_Z7testllff
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; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1
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; CHECK: mfvsrd 3, [[CONVREG13]]
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}
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; Function Attrs: nounwind
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define float @_Z7testfllx(i64 %arg) {
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entry:
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%arg.addr = alloca i64, align 8
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store i64 %arg, i64* %arg.addr, align 8
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%0 = load i64, i64* %arg.addr, align 8
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%conv = sitofp i64 %0 to float
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ret float %conv
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; CHECK-LABEL:@_Z7testfllx
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; CHECK: mtvsrd [[MOVEREG13:[0-9]+]], 3
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; CHECK: xscvsxdsp 1, [[MOVEREG13]]
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}
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; Function Attrs: nounwind
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define i64 @_Z7testlldd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptosi double %0 to i64
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ret i64 %conv
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; CHECK-LABEL: @_Z7testlldd
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; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1
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; CHECK: mfvsrd 3, [[CONVREG14]]
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}
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; Function Attrs: nounwind
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define double @_Z7testdllx(i64 %arg) {
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entry:
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%arg.addr = alloca i64, align 8
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store i64 %arg, i64* %arg.addr, align 8
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%0 = load i64, i64* %arg.addr, align 8
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%conv = sitofp i64 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z7testdllx
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; CHECK: mtvsrd [[MOVEREG14:[0-9]+]], 3
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; CHECK: xscvsxddp 1, [[MOVEREG14]]
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}
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; Function Attrs: nounwind
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define i64 @_Z8testullff(float %arg) {
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entry:
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%arg.addr = alloca float, align 4
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store float %arg, float* %arg.addr, align 4
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%0 = load float, float* %arg.addr, align 4
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%conv = fptoui float %0 to i64
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ret i64 %conv
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; CHECK-LABEL: @_Z8testullff
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; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1
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; CHECK: mfvsrd 3, [[CONVREG15]]
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}
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; Function Attrs: nounwind
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define float @_Z8testfully(i64 %arg) {
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entry:
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%arg.addr = alloca i64, align 8
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store i64 %arg, i64* %arg.addr, align 8
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%0 = load i64, i64* %arg.addr, align 8
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%conv = uitofp i64 %0 to float
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ret float %conv
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; CHECK-LABEL: @_Z8testfully
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; CHECK: mtvsrd [[MOVEREG15:[0-9]+]], 3
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; CHECK: xscvuxdsp 1, [[MOVEREG15]]
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}
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; Function Attrs: nounwind
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define i64 @_Z8testulldd(double %arg) {
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entry:
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%arg.addr = alloca double, align 8
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store double %arg, double* %arg.addr, align 8
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%0 = load double, double* %arg.addr, align 8
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%conv = fptoui double %0 to i64
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ret i64 %conv
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; CHECK-LABEL: @_Z8testulldd
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; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1
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; CHECK: mfvsrd 3, [[CONVREG16]]
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}
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; Function Attrs: nounwind
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define double @_Z8testdully(i64 %arg) {
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entry:
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%arg.addr = alloca i64, align 8
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store i64 %arg, i64* %arg.addr, align 8
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%0 = load i64, i64* %arg.addr, align 8
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%conv = uitofp i64 %0 to double
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ret double %conv
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; CHECK-LABEL: @_Z8testdully
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; CHECK: mtvsrd [[MOVEREG16:[0-9]+]], 3
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; CHECK: xscvuxddp 1, [[MOVEREG16]]
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}
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