forked from OSchip/llvm-project
152 lines
2.9 KiB
LLVM
152 lines
2.9 KiB
LLVM
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
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define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: daddu
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%add = add nsw i64 %a1, %a0
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ret i64 %add
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}
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define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dsubu
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%sub = sub nsw i64 %a0, %a1
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ret i64 %sub
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}
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define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: and
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%and = and i64 %a1, %a0
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ret i64 %and
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}
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define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: or
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%or = or i64 %a1, %a0
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ret i64 %or
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}
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define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: xor
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%xor = xor i64 %a1, %a0
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ret i64 %xor
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}
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define i64 @f7(i64 %a0) nounwind readnone {
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entry:
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; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20
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%add = add nsw i64 %a0, 20
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ret i64 %add
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}
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define i64 @f8(i64 %a0) nounwind readnone {
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entry:
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; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20
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%sub = add nsw i64 %a0, -20
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ret i64 %sub
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}
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define i64 @f9(i64 %a0) nounwind readnone {
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entry:
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; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20
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%and = and i64 %a0, 20
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ret i64 %and
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}
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define i64 @f10(i64 %a0) nounwind readnone {
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entry:
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; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20
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%or = or i64 %a0, 20
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ret i64 %or
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}
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define i64 @f11(i64 %a0) nounwind readnone {
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entry:
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; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20
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%xor = xor i64 %a0, 20
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ret i64 %xor
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}
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define i64 @f12(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: mult
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%mul = mul nsw i64 %b, %a
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ret i64 %mul
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}
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define i64 @f13(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: mult
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%mul = mul i64 %b, %a
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ret i64 %mul
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}
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define i64 @f14(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f14:
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; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mflo
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%div = sdiv i64 %a, %b
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ret i64 %div
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}
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define i64 @f15(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f15:
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; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mflo
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%div = udiv i64 %a, %b
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ret i64 %div
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}
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define i64 @f16(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f16:
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; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mfhi
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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define i64 @f17(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f17:
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; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mfhi
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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define i64 @f18(i64 %X) nounwind readnone {
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entry:
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; CHECK: dclz $2, $4
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
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ret i64 %tmp1
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}
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define i64 @f19(i64 %X) nounwind readnone {
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entry:
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; CHECK: dclo $2, $4
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%neg = xor i64 %X, -1
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
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ret i64 %tmp1
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}
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define i64 @f20(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: nor
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%or = or i64 %b, %a
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%neg = xor i64 %or, -1
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ret i64 %neg
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}
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