llvm-project/llvm/test/CodeGen
Craig Topper 3da269a248 [X86] Add a DAG combine to turn (and (bitcast (vXi1 (concat_vectors (vYi1 setcc), undef,))), C) into (bitcast (vXi1 (concat_vectors (vYi1 setcc), zero,)))
The legalization of v2i1->i2 or v4i1->i4 bitcasts followed by a setcc can create an and after the bitcast. If we're lucky enough that the input to the bitcast is a concat_vectors where the first operand is a setcc that can natively 0 all the upper bits of ak-register, then we should replace the other operands of the concat_vectors with zero in order to remove the AND.

With the AND removed we might be able to use a kortest on the result.

Differential Revision: https://reviews.llvm.org/D69205
2019-10-28 11:27:01 -07:00
..
AArch64 Reland [AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2) 2019-10-28 18:05:19 +00:00
AMDGPU AMDGPU: Avoid overwriting saved PC 2019-10-28 10:02:22 -07:00
ARC
ARM Add Windows Control Flow Guard checks (/guard:cf). 2019-10-28 15:19:39 +00:00
AVR
BPF [BPF] fix a CO-RE issue with -mattr=+alu32 2019-10-25 14:27:25 -07:00
Generic Reapply r374743 with a fix for the ocaml binding 2019-10-14 16:15:14 +00:00
Hexagon [DFAPacketizer] Use DFAEmitter. NFC. 2019-10-17 08:34:29 +00:00
Inputs
Lanai
MIR [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
MSP430 [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2) 2019-10-19 16:57:02 +00:00
Mips [MIPS GlobalISel] Select MSA vector generic and builtin fsqrt 2019-10-25 14:45:14 +02:00
NVPTX [NVPTX] Restructure shfl instrinsics and add variants that return a predicate. 2019-10-14 16:53:34 +00:00
PowerPC [AIX] Refactor AIX Call Lowering to use CCState. NFCI. 2019-10-28 12:44:22 -04:00
RISCV [RISCV] Lower llvm.trap and llvm.debugtrap 2019-10-28 09:54:33 +00:00
SPARC
SystemZ [FPEnv] Strict FP tests should use the requisite function attributes. 2019-10-04 17:03:46 +00:00
Thumb (Re)generate various tests. NFC 2019-10-08 16:16:26 +00:00
Thumb2 [InstCombine] Known-bits optimization for ARM MVE VADC. 2019-10-24 16:33:13 +01:00
WebAssembly [SDAG] fold insert_vector_elt with undef index 2019-10-27 15:28:43 -04:00
WinCFGuard Add Windows Control Flow Guard checks (/guard:cf). 2019-10-28 15:19:39 +00:00
WinEH
X86 [X86] Add a DAG combine to turn (and (bitcast (vXi1 (concat_vectors (vYi1 setcc), undef,))), C) into (bitcast (vXi1 (concat_vectors (vYi1 setcc), zero,))) 2019-10-28 11:27:01 -07:00
XCore