forked from OSchip/llvm-project
51 lines
1.4 KiB
LLVM
51 lines
1.4 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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;
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@a = global double 0.0, align 4
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@b = global double 0.0, align 4
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@c = global double 0.0, align 4
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; CHECK: ********** MI Scheduling **********
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; We need second, post-ra scheduling to have VLDM instruction combined from single-loads
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; CHECK: ********** MI Scheduling **********
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; CHECK: VLDMDIA_UPD
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 6
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; CHECK: Successors:
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; CHECK: Data
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; CHECK-SAME: Latency=1
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; CHECK-NEXT: Data
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; CHECK-SAME: Latency=1
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; CHECK-NEXT: Data
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; CHECK-SAME: Latency=5
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; CHECK-NEXT: Data
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; CHECK-SAME: Latency=5
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; CHECK-NEXT: Data
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; CHECK-SAME: Latency=6
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define i32 @bar(i32* %iptr) minsize optsize {
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%1 = load double, double* @a, align 8
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%2 = load double, double* @b, align 8
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%3 = load double, double* @c, align 8
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%ptr_after = getelementptr double, double* @a, i32 3
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%ptr_new_ival = ptrtoint double* %ptr_after to i32
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%ptr_new = inttoptr i32 %ptr_new_ival to i32*
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store i32 %ptr_new_ival, i32* %iptr, align 8
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%v1 = fptoui double %1 to i32
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%mul1 = mul i32 %ptr_new_ival, %v1
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%v2 = fptoui double %2 to i32
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%v3 = fptoui double %3 to i32
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%mul2 = mul i32 %mul1, %v2
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%mul3 = mul i32 %mul2, %v3
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ret i32 %mul3
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}
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