forked from OSchip/llvm-project
106 lines
4.0 KiB
YAML
106 lines
4.0 KiB
YAML
# RUN: llc -o - %s -mtriple=amdgcn-- -mcpu=fiji -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s
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--- |
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define amdgpu_kernel void @func0() #0 { ret void }
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define amdgpu_kernel void @func1() #0 { ret void }
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define amdgpu_kernel void @splitHoist() #0 { ret void }
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attributes #0 = { "amdgpu-num-sgpr"="12" }
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...
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---
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# Make sure we only get a single spill+reload even if liverange splitting
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# created a sequence of multiple copy instructions.
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# CHECK-LABEL: name: func0
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# CHECK: SI_SPILL_S128_SAVE
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# CHECK-NOT: SI_SPILL_S128_SAVE
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# CHECK: S_NOP 0
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# CHECK: SI_SPILL_S128_RESTORE
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# CHECK-NOT: SI_SPILL_S128_RESTORE
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name: func0
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body: |
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bb.0:
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S_NOP 0, implicit-def undef %0.sub0 : sreg_128
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S_NOP 0, implicit-def %0.sub3 : sreg_128
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; Clobber registers
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S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
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S_NOP 0, implicit %0.sub0
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S_NOP 0, implicit %0.sub3
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S_NOP 0, implicit %0.sub0
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S_NOP 0, implicit %0.sub3
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...
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---
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# LiveRange splitting should split this into 2 intervals with the second getting
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# allocated to sgpr0_sgpr1 and the first to something else so we see two copies
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# in between for the two subregisters that are alive.
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# CHECK-LABEL: name: func1
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# CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0
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# CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2
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# CHECK: S_NOP 0
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# CHECK: S_NOP 0, implicit [[REG0]]
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# CHECK: S_NOP 0, implicit [[REG1]]
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# CHECK: %sgpr0 = COPY [[REG0]]
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# CHECK: %sgpr2 = COPY [[REG1]]
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# CHECK: S_NOP
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# CHECK: S_NOP 0, implicit %sgpr0
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# CHECK: S_NOP 0, implicit %sgpr2
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name: func1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: %sgpr0, %sgpr1, %sgpr2
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undef %0.sub0 : sreg_128 = COPY %sgpr0
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%0.sub2 = COPY %sgpr2
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S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1
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S_NOP 0, implicit %0.sub0
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S_NOP 0, implicit %0.sub2
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; Clobber everything but sgpr0-sgpr3
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S_NOP 0, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11, implicit-def dead %sgpr12, implicit-def dead %sgpr13, implicit-def dead %sgpr14, implicit-def dead %sgpr15, implicit-def dead %vcc_lo, implicit-def dead %vcc_hi
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S_NOP 0, implicit %0.sub0
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S_NOP 0, implicit %0.sub2
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...
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---
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# Check that copy hoisting out of loops works. This mainly should not crash the
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# compiler when it hoists a subreg copy sequence.
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# CHECK-LABEL: name: splitHoist
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# CHECK: S_NOP 0, implicit-def %sgpr0
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# CHECK: S_NOP 0, implicit-def %sgpr3
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# CHECK-NEXT: SI_SPILL_S128_SAVE
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name: splitHoist
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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S_NOP 0, implicit-def undef %0.sub0 : sreg_128
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S_NOP 0, implicit-def %0.sub3 : sreg_128
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.1, %bb.3
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S_NOP 0, implicit %0.sub0
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; Clobber registers
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S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
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S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3
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; Clobber registers
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S_NOP 0, implicit-def dead %sgpr0, implicit-def dead %sgpr1, implicit-def dead %sgpr2, implicit-def dead %sgpr3, implicit-def dead %sgpr4, implicit-def dead %sgpr5, implicit-def dead %sgpr6, implicit-def dead %sgpr7, implicit-def dead %sgpr8, implicit-def dead %sgpr9, implicit-def dead %sgpr10, implicit-def dead %sgpr11
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S_BRANCH %bb.3
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bb.3:
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S_NOP 0, implicit %0.sub0
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S_NOP 0, implicit %0.sub3
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S_NOP 0, implicit %0.sub0
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S_NOP 0, implicit %0.sub3
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...
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