forked from OSchip/llvm-project
130 lines
4.6 KiB
LLVM
130 lines
4.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)
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; GCN-LABEL: {{^}}div_fixup_f16
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b,
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half addrspace(1)* %c) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%c.val = load half, half addrspace(1)* %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half %c.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_a
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x4200{{$}}
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_a(
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half addrspace(1)* %r,
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half addrspace(1)* %b,
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half addrspace(1)* %c) {
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entry:
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%b.val = load half, half addrspace(1)* %b
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%c.val = load half, half addrspace(1)* %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half %c.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_b
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x4200{{$}}
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_b(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %c) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%c.val = load half, half addrspace(1)* %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half %c.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_c
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x4200{{$}}
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_c(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half 3.0)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_b
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; VI: v_mov_b32_e32 v[[AB_F16:[0-9]+]], 0x4200{{$}}
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[AB_F16]], v[[AB_F16]], v[[C_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_a_imm_b(
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half addrspace(1)* %r,
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half addrspace(1)* %c) {
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entry:
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%c.val = load half, half addrspace(1)* %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half 3.0, half %c.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_b_imm_c
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; VI: v_mov_b32_e32 v[[BC_F16:[0-9]+]], 0x4200{{$}}
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[A_F16]], v[[BC_F16]], v[[BC_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_b_imm_c(
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half addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half 3.0)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}div_fixup_f16_imm_a_imm_c
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; VI: v_mov_b32_e32 v[[AC_F16:[0-9]+]], 0x4200{{$}}
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; VI: v_div_fixup_f16 v[[R_F16:[0-9]+]], v[[AC_F16]], v[[B_F16]], v[[AC_F16]]
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; GCN: buffer_store_short v[[R_F16]]
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; GCN: s_endpgm
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define amdgpu_kernel void @div_fixup_f16_imm_a_imm_c(
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half addrspace(1)* %r,
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half addrspace(1)* %b) {
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entry:
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%b.val = load half, half addrspace(1)* %b
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half 3.0)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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