forked from OSchip/llvm-project
149 lines
5.7 KiB
C++
149 lines
5.7 KiB
C++
//==-- SystemZISelLowering.h - SystemZ DAG Lowering Interface ----*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that SystemZ uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
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#define LLVM_TARGET_SystemZ_ISELLOWERING_H
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#include "SystemZ.h"
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#include "SystemZRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace SystemZISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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/// Return with a flag operand. Operand 0 is the chain operand.
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RET_FLAG,
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/// CALL - These operations represent an abstract call
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/// instruction, which includes a bunch of information.
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CALL,
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/// PCRelativeWrapper - PC relative address
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PCRelativeWrapper,
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/// CMP, UCMP - Compare instruction
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CMP,
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UCMP,
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/// BRCOND - Conditional branch. Operand 0 is chain operand, operand 1 is
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/// the block to branch if condition is true, operand 2 is condition code
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/// and operand 3 is the flag operand produced by a CMP instruction.
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BRCOND,
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/// SELECT - Operands 0 and 1 are selection variables, operand 2 is
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/// condition code and operand 3 is the flag operand.
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SELECT
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};
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}
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class SystemZSubtarget;
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class SystemZTargetMachine;
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class SystemZTargetLowering : public TargetLowering {
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public:
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explicit SystemZTargetLowering(SystemZTargetMachine &TM);
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const {
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return 1;
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}
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
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TargetLowering::ConstraintType
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getConstraintType(const std::string &Constraint) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue EmitCmp(SDValue LHS, SDValue RHS,
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ISD::CondCode CC, SDValue &SystemZCC,
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SelectionDAG &DAG) const;
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MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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private:
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SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCCCArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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const SystemZSubtarget &Subtarget;
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const SystemZTargetMachine &TM;
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const SystemZRegisterInfo *RegInfo;
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};
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} // namespace llvm
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#endif // LLVM_TARGET_SystemZ_ISELLOWERING_H
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