llvm-project/llvm/test/Transforms/IRCE
Max Kazantsev 2c627a97fd [IRCE] Recognize loops with ne/eq latch conditions
In some particular cases eq/ne conditions can be turned into equivalent
slt/sgt conditions. This patch teaches parseLoopStructure to handle some
of these cases.

Differential Revision: https://reviews.llvm.org/D35010

llvm-svn: 308264
2017-07-18 04:53:48 +00:00
..
add-metadata-pre-post-loops.ll
bad-loop-structure.ll [IRCE] Add a missing invariant check 2017-02-07 23:59:07 +00:00
bug-loop-varying-upper-limit.ll
bug-mismatched-types.ll
conjunctive-checks.ll
correct-loop-info.ll [IRCE] Canonicalize pre/post loops after the blocks are added into parent loop 2017-06-06 14:54:01 +00:00
decrementing-loop.ll
eq_ne.ll [IRCE] Recognize loops with ne/eq latch conditions 2017-07-18 04:53:48 +00:00
low-becount.ll
multiple-access-no-preloop.ll
not-likely-taken.ll
only-lower-check.ll
only-upper-check.ll
pre_post_loops.ll [IRCE] Fix corner case with Start = INT_MAX 2017-07-14 06:35:03 +00:00
single-access-no-preloop.ll
single-access-with-preloop.ll
skip-profitability-checks.ll
unhandled.ll
with-parent-loops.ll