forked from OSchip/llvm-project
8e82af2be6
Summary: Now that we have control flow in place, fuse the per-rule tables into a single table. This is a compile-time saving at this point. However, this will also enable the optimization of a table so that similar instructions can be tested together, reducing the time spent on the matching the code. This is NFC in terms of externally visible behaviour but some internals have changed slightly. State.MIs is no longer reset between each rule that is attempted because it's not necessary to do so. As a consequence of this the restriction on the order that instructions are added to State.MIs has been relaxed to only affect recorded instructions that require new elements to be added to the vector. GIM_RecordInsn can now write to any element from 1 to State.MIs.size() instead of just State.MIs.size(). The compile-time regressions from the last commit were caused by the ARM target including a non-const variable (zero_reg) in the table and therefore generating an initializer for it. That variable is now const. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35681 llvm-svn: 309264 |
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| .. | ||
| 2003-08-03-PassCode.td | ||
| 2006-09-18-LargeInt.td | ||
| 2010-03-24-PrematureDefaults.td | ||
| AnonDefinitionOnDemand.td | ||
| AsmPredicateCondsEmission.td | ||
| AsmVariant.td | ||
| BitOffsetDecoder.td | ||
| BitsInit.td | ||
| BitsInitOverflow.td | ||
| CStyleComment.td | ||
| ClassInstanceValue.td | ||
| Dag.td | ||
| DefmInherit.td | ||
| DefmInsideMultiClass.td | ||
| DuplicateFieldValues.td | ||
| FieldAccess.td | ||
| ForeachList.td | ||
| ForeachLoop.td | ||
| ForwardRef.td | ||
| GeneralList.td | ||
| GlobalISelEmitter.td | ||
| Include.inc | ||
| Include.td | ||
| IntBitInit.td | ||
| LazyChange.td | ||
| LetInsideMultiClasses.td | ||
| ListArgs.td | ||
| ListArgsSimple.td | ||
| ListConversion.td | ||
| ListManip.td | ||
| ListOfList.td | ||
| ListSlices.td | ||
| LoLoL.td | ||
| MultiClass.td | ||
| MultiClassDefName.td | ||
| MultiClassInherit.td | ||
| MultiPat.td | ||
| NestedForeach.td | ||
| Paste.td | ||
| RegisterBankEmitter.td | ||
| RegisterEncoder.td | ||
| SetTheory.td | ||
| SiblingForeach.td | ||
| Slice.td | ||
| String.td | ||
| SuperSubclassSameName.td | ||
| TargetInstrInfo.td | ||
| TargetInstrSpec.td | ||
| TemplateArgRename.td | ||
| Tree.td | ||
| TreeNames.td | ||
| TwoLevelName.td | ||
| UnsetBitInit.td | ||
| UnterminatedComment.td | ||
| ValidIdentifiers.td | ||
| cast-list-initializer.td | ||
| cast.td | ||
| defmclass.td | ||
| eq.td | ||
| eqbit.td | ||
| foreach.td | ||
| if-empty-list-arg.td | ||
| if.td | ||
| ifbit.td | ||
| intrinsic-long-name.td | ||
| intrinsic-varargs.td | ||
| lisp.td | ||
| list-element-bitref.td | ||
| listconcat.td | ||
| lit.local.cfg | ||
| math.td | ||
| nested-comment.td | ||
| pr8330.td | ||
| strconcat.td | ||
| subst.td | ||
| subst2.td | ||
| trydecode-emission.td | ||
| trydecode-emission2.td | ||
| trydecode-emission3.td | ||
| usevalname.td | ||