forked from OSchip/llvm-project
273 lines
11 KiB
TableGen
273 lines
11 KiB
TableGen
// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// WebAssembly Instruction definitions.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
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def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
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def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
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AssemblerPredicate<"FeatureSIMD128", "simd128">;
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def HasAtomics : Predicate<"Subtarget->hasAtomics()">,
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AssemblerPredicate<"FeatureAtomics", "atomics">;
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def HasNontrappingFPToInt :
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Predicate<"Subtarget->hasNontrappingFPToInt()">,
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AssemblerPredicate<"FeatureNontrappingFPToInt",
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"nontrapping-fptoint">;
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def NotHasNontrappingFPToInt :
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Predicate<"!Subtarget->hasNontrappingFPToInt()">,
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AssemblerPredicate<"!FeatureNontrappingFPToInt",
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"nontrapping-fptoint">;
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def HasSignExt :
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Predicate<"Subtarget->hasSignExt()">,
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AssemblerPredicate<"FeatureSignExt",
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"sign-ext">;
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def NotHasSignExt :
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Predicate<"!Subtarget->hasSignExt()">,
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AssemblerPredicate<"!FeatureSignExt",
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"sign-ext">;
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def HasExceptionHandling :
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Predicate<"Subtarget->hasExceptionHandling()">,
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AssemblerPredicate<"FeatureExceptionHandling",
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"exception-handling">;
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def NotHasExceptionHandling :
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Predicate<"!Subtarget->hasExceptionHandling()">,
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AssemblerPredicate<"!FeatureExceptionHandling",
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"exception-handling">;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Node Types.
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//===----------------------------------------------------------------------===//
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def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
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SDTCisVT<1, iPTR>]>;
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def SDT_WebAssemblyCallSeqEnd :
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SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
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def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
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def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
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def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
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def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
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SDTCisPtrTy<0>]>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def WebAssemblycallseq_start :
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SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def WebAssemblycallseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0",
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SDT_WebAssemblyCall0,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
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SDT_WebAssemblyCall1,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE",
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SDT_WebAssemblyBrTable,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
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SDT_WebAssemblyArgument>;
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def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
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SDT_WebAssemblyReturn, [SDNPHasChain]>;
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def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper",
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SDT_WebAssemblyWrapper>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific Operands.
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//===----------------------------------------------------------------------===//
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let OperandNamespace = "WebAssembly" in {
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let OperandType = "OPERAND_BASIC_BLOCK" in
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def bb_op : Operand<OtherVT>;
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let OperandType = "OPERAND_LOCAL" in
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def local_op : Operand<i32>;
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let OperandType = "OPERAND_GLOBAL" in
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def global_op : Operand<i32>;
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let OperandType = "OPERAND_I32IMM" in
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def i32imm_op : Operand<i32>;
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let OperandType = "OPERAND_I64IMM" in
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def i64imm_op : Operand<i64>;
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let OperandType = "OPERAND_F32IMM" in
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def f32imm_op : Operand<f32>;
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let OperandType = "OPERAND_F64IMM" in
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def f64imm_op : Operand<f64>;
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let OperandType = "OPERAND_FUNCTION32" in
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def function32_op : Operand<i32>;
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let OperandType = "OPERAND_OFFSET32" in
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def offset32_op : Operand<i32>;
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let OperandType = "OPERAND_P2ALIGN" in {
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def P2Align : Operand<i32> {
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let PrintMethod = "printWebAssemblyP2AlignOperand";
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}
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} // OperandType = "OPERAND_P2ALIGN"
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let OperandType = "OPERAND_SIGNATURE" in {
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def Signature : Operand<i32> {
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let PrintMethod = "printWebAssemblySignatureOperand";
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}
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} // OperandType = "OPERAND_SIGNATURE"
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let OperandType = "OPERAND_TYPEINDEX" in
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def TypeIndex : Operand<i32>;
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} // OperandNamespace = "WebAssembly"
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Format Definitions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Additional instructions.
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//===----------------------------------------------------------------------===//
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multiclass ARGUMENT<WebAssemblyRegClass vt> {
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let hasSideEffects = 1, Uses = [ARGUMENTS], isCodeGenOnly = 1 in
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def ARGUMENT_#vt : I<(outs vt:$res), (ins i32imm:$argno),
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[(set vt:$res, (WebAssemblyargument timm:$argno))]>;
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}
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multiclass SIMD_ARGUMENT<ValueType vt> {
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let hasSideEffects = 1, Uses = [ARGUMENTS], isCodeGenOnly = 1 in
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def ARGUMENT_#vt : SIMD_I<(outs V128:$res), (ins i32imm:$argno),
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[(set (vt V128:$res),
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(WebAssemblyargument timm:$argno))]>;
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}
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defm "": ARGUMENT<I32>;
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defm "": ARGUMENT<I64>;
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defm "": ARGUMENT<F32>;
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defm "": ARGUMENT<F64>;
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defm "": ARGUMENT<EXCEPT_REF>;
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defm "": SIMD_ARGUMENT<v16i8>;
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defm "": SIMD_ARGUMENT<v8i16>;
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defm "": SIMD_ARGUMENT<v4i32>;
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defm "": SIMD_ARGUMENT<v4f32>;
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let Defs = [ARGUMENTS] in {
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// get_local and set_local are not generated by instruction selection; they
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// are implied by virtual register uses and defs.
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multiclass LOCAL<WebAssemblyRegClass vt> {
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let hasSideEffects = 0 in {
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// COPY is not an actual instruction in wasm, but since we allow get_local and
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// set_local to be implicit during most of codegen, we can have a COPY which
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// is actually a no-op because all the work is done in the implied get_local
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// and set_local. COPYs are eliminated (and replaced with
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// get_local/set_local) in the ExplicitLocals pass.
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let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
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def COPY_#vt : I<(outs vt:$res), (ins vt:$src), [], "copy_local\t$res, $src">;
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// TEE is similar to COPY, but writes two copies of its result. Typically
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// this would be used to stackify one result and write the other result to a
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// local.
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let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
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def TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), [],
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"tee_local\t$res, $also, $src">;
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// This is the actual get_local instruction in wasm. These are made explicit
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// by the ExplicitLocals pass. It has mayLoad because it reads from a wasm
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// local, which is a side effect not otherwise modeled in LLVM.
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let mayLoad = 1, isAsCheapAsAMove = 1 in
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def GET_LOCAL_#vt : I<(outs vt:$res), (ins local_op:$local), [],
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"get_local\t$res, $local", 0x20>;
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// This is the actual set_local instruction in wasm. These are made explicit
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// by the ExplicitLocals pass. It has mayStore because it writes to a wasm
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// local, which is a side effect not otherwise modeled in LLVM.
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let mayStore = 1, isAsCheapAsAMove = 1 in
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def SET_LOCAL_#vt : I<(outs), (ins local_op:$local, vt:$src), [],
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"set_local\t$local, $src", 0x21>;
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// This is the actual tee_local instruction in wasm. TEEs are turned into
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// TEE_LOCALs by the ExplicitLocals pass. It has mayStore for the same reason
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// as SET_LOCAL.
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let mayStore = 1, isAsCheapAsAMove = 1 in
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def TEE_LOCAL_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src), [],
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"tee_local\t$res, $local, $src", 0x22>;
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// Unused values must be dropped in some contexts.
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def DROP_#vt : I<(outs), (ins vt:$src), [],
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"drop\t$src", 0x1a>;
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let mayLoad = 1 in
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def GET_GLOBAL_#vt : I<(outs vt:$res), (ins global_op:$local), [],
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"get_global\t$res, $local", 0x23>;
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let mayStore = 1 in
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def SET_GLOBAL_#vt : I<(outs), (ins global_op:$local, vt:$src), [],
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"set_global\t$local, $src", 0x24>;
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} // hasSideEffects = 0
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}
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defm "" : LOCAL<I32>;
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defm "" : LOCAL<I64>;
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defm "" : LOCAL<F32>;
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defm "" : LOCAL<F64>;
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defm "" : LOCAL<V128>, Requires<[HasSIMD128]>;
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defm "" : LOCAL<EXCEPT_REF>, Requires<[HasExceptionHandling]>;
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let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
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def CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
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[(set I32:$res, imm:$imm)],
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"i32.const\t$res, $imm", 0x41>;
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def CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm),
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[(set I64:$res, imm:$imm)],
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"i64.const\t$res, $imm", 0x42>;
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def CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm),
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[(set F32:$res, fpimm:$imm)],
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"f32.const\t$res, $imm", 0x43>;
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def CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm),
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[(set F64:$res, fpimm:$imm)],
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"f64.const\t$res, $imm", 0x44>;
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} // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1
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} // Defs = [ARGUMENTS]
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def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)),
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(CONST_I32 tglobaladdr:$addr)>;
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def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)),
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(CONST_I32 texternalsym:$addr)>;
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//===----------------------------------------------------------------------===//
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// Additional sets of instructions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrMemory.td"
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include "WebAssemblyInstrCall.td"
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include "WebAssemblyInstrControl.td"
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include "WebAssemblyInstrInteger.td"
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include "WebAssemblyInstrConv.td"
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include "WebAssemblyInstrFloat.td"
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include "WebAssemblyInstrAtomics.td"
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include "WebAssemblyInstrSIMD.td"
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include "WebAssemblyInstrExceptRef.td"
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