forked from OSchip/llvm-project
988 lines
26 KiB
C++
988 lines
26 KiB
C++
//=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
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#include "AMDGPU.h"
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#include "AMDGPUCallLowering.h"
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#include "R600FrameLowering.h"
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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#include "SIFrameLowering.h"
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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#include <cstdint>
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#include <memory>
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#include <utility>
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#define GET_SUBTARGETINFO_HEADER
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#include "AMDGPUGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
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public:
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enum Generation {
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R600 = 0,
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R700,
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EVERGREEN,
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NORTHERN_ISLANDS,
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SOUTHERN_ISLANDS,
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SEA_ISLANDS,
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VOLCANIC_ISLANDS,
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GFX9,
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};
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enum {
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ISAVersion0_0_0,
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ISAVersion6_0_0,
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ISAVersion6_0_1,
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ISAVersion7_0_0,
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ISAVersion7_0_1,
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ISAVersion7_0_2,
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ISAVersion7_0_3,
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ISAVersion7_0_4,
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ISAVersion8_0_1,
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ISAVersion8_0_2,
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ISAVersion8_0_3,
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ISAVersion8_1_0,
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ISAVersion9_0_0,
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ISAVersion9_0_2,
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ISAVersion9_0_4,
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ISAVersion9_0_6,
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};
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enum TrapHandlerAbi {
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TrapHandlerAbiNone = 0,
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TrapHandlerAbiHsa = 1
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};
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enum TrapID {
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TrapIDHardwareReserved = 0,
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TrapIDHSADebugTrap = 1,
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TrapIDLLVMTrap = 2,
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TrapIDLLVMDebugTrap = 3,
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TrapIDDebugBreakpoint = 7,
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TrapIDDebugReserved8 = 8,
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TrapIDDebugReservedFE = 0xfe,
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TrapIDDebugReservedFF = 0xff
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};
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enum TrapRegValues {
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LLVMTrapHandlerRegValue = 1
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};
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protected:
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// Basic subtarget description.
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Triple TargetTriple;
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Generation Gen;
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unsigned IsaVersion;
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unsigned WavefrontSize;
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int LocalMemorySize;
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int LDSBankCount;
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unsigned MaxPrivateElementSize;
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// Possibly statically set by tablegen, but may want to be overridden.
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bool FastFMAF32;
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bool HalfRate64Ops;
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// Dynamially set bits that enable features.
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bool FP32Denormals;
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bool FP64FP16Denormals;
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bool FPExceptions;
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bool DX10Clamp;
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bool FlatForGlobal;
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bool AutoWaitcntBeforeBarrier;
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bool CodeObjectV3;
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bool UnalignedScratchAccess;
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bool UnalignedBufferAccess;
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bool HasApertureRegs;
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bool EnableXNACK;
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bool TrapHandler;
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bool DebuggerInsertNops;
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bool DebuggerReserveRegs;
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bool DebuggerEmitPrologue;
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// Used as options.
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bool EnableHugePrivateBuffer;
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bool EnableVGPRSpilling;
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bool EnablePromoteAlloca;
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bool EnableLoadStoreOpt;
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bool EnableUnsafeDSOffsetFolding;
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bool EnableSIScheduler;
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bool EnableDS128;
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bool DumpCode;
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// Subtarget statically properties set by tablegen
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bool FP64;
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bool FMA;
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bool MIMG_R128;
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bool IsGCN;
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bool GCN3Encoding;
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bool CIInsts;
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bool GFX9Insts;
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bool SGPRInitBug;
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bool HasSMemRealTime;
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bool Has16BitInsts;
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bool HasIntClamp;
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bool HasVOP3PInsts;
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bool HasMadMixInsts;
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bool HasFmaMixInsts;
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bool HasMovrel;
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bool HasVGPRIndexMode;
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bool HasScalarStores;
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bool HasScalarAtomics;
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bool HasInv2PiInlineImm;
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bool HasSDWA;
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bool HasSDWAOmod;
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bool HasSDWAScalar;
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bool HasSDWASdst;
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bool HasSDWAMac;
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bool HasSDWAOutModsVOPC;
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bool HasDPP;
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bool HasDLInsts;
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bool D16PreservesUnusedBits;
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bool FlatAddressSpace;
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bool FlatInstOffsets;
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bool FlatGlobalInsts;
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bool FlatScratchInsts;
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bool AddNoCarryInsts;
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bool HasUnpackedD16VMem;
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bool R600ALUInst;
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bool CaymanISA;
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bool CFALUBug;
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bool HasVertexCache;
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short TexVTXClauseSize;
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bool ScalarizeGlobal;
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// Dummy feature to use for assembler in tablegen.
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bool FeatureDisable;
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InstrItineraryData InstrItins;
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SelectionDAGTargetInfo TSInfo;
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AMDGPUAS AS;
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public:
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AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const TargetMachine &TM);
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~AMDGPUSubtarget() override;
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AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef GPU, StringRef FS);
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const AMDGPUInstrInfo *getInstrInfo() const override = 0;
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const AMDGPUFrameLowering *getFrameLowering() const override = 0;
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const AMDGPUTargetLowering *getTargetLowering() const override = 0;
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const AMDGPURegisterInfo *getRegisterInfo() const override = 0;
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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// Nothing implemented, just prevent crashes on use.
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool isAmdHsaOS() const {
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return TargetTriple.getOS() == Triple::AMDHSA;
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}
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bool isMesa3DOS() const {
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return TargetTriple.getOS() == Triple::Mesa3D;
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}
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bool isAmdPalOS() const {
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return TargetTriple.getOS() == Triple::AMDPAL;
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}
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Generation getGeneration() const {
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return Gen;
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}
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unsigned getWavefrontSize() const {
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return WavefrontSize;
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}
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unsigned getWavefrontSizeLog2() const {
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return Log2_32(WavefrontSize);
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}
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int getLocalMemorySize() const {
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return LocalMemorySize;
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}
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int getLDSBankCount() const {
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return LDSBankCount;
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}
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unsigned getMaxPrivateElementSize() const {
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return MaxPrivateElementSize;
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}
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AMDGPUAS getAMDGPUAS() const {
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return AS;
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}
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bool has16BitInsts() const {
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return Has16BitInsts;
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}
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bool hasIntClamp() const {
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return HasIntClamp;
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}
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bool hasVOP3PInsts() const {
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return HasVOP3PInsts;
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}
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bool hasFP64() const {
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return FP64;
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}
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bool hasMIMG_R128() const {
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return MIMG_R128;
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}
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bool hasFastFMAF32() const {
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return FastFMAF32;
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}
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bool hasHalfRate64Ops() const {
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return HalfRate64Ops;
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}
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bool hasAddr64() const {
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return (getGeneration() < VOLCANIC_ISLANDS);
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}
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFI() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFM() const {
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return hasBFE();
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}
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bool hasBCNT(unsigned Size) const {
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if (Size == 32)
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return (getGeneration() >= EVERGREEN);
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if (Size == 64)
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return (getGeneration() >= SOUTHERN_ISLANDS);
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return false;
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}
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bool hasMulU24() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasMulI24() const {
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return (getGeneration() >= SOUTHERN_ISLANDS ||
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hasCaymanISA());
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}
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bool hasFFBL() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasFFBH() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasMed3_16() const {
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return getGeneration() >= GFX9;
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}
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bool hasMin3Max3_16() const {
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return getGeneration() >= GFX9;
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}
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bool hasMadMixInsts() const {
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return HasMadMixInsts;
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}
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bool hasFmaMixInsts() const {
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return HasFmaMixInsts;
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}
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bool hasCARRY() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBORROW() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasCaymanISA() const {
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return CaymanISA;
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}
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bool hasFMA() const {
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return FMA;
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}
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TrapHandlerAbi getTrapHandlerAbi() const {
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return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
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}
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bool enableHugePrivateBuffer() const {
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return EnableHugePrivateBuffer;
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}
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bool isPromoteAllocaEnabled() const {
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return EnablePromoteAlloca;
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}
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bool unsafeDSOffsetFoldingEnabled() const {
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return EnableUnsafeDSOffsetFolding;
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}
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bool dumpCode() const {
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return DumpCode;
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}
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/// Return the amount of LDS that can be used that will not restrict the
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/// occupancy lower than WaveCount.
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unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
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const Function &) const;
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/// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
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/// the given LDS memory size is the only constraint.
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unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
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unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const;
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bool hasFP16Denormals() const {
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return FP64FP16Denormals;
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}
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bool hasFP32Denormals() const {
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return FP32Denormals;
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}
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bool hasFP64Denormals() const {
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return FP64FP16Denormals;
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}
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bool supportsMinMaxDenormModes() const {
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return getGeneration() >= AMDGPUSubtarget::GFX9;
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}
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bool hasFPExceptions() const {
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return FPExceptions;
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}
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bool enableDX10Clamp() const {
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return DX10Clamp;
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}
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bool enableIEEEBit(const MachineFunction &MF) const {
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return AMDGPU::isCompute(MF.getFunction().getCallingConv());
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}
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bool useFlatForGlobal() const {
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return FlatForGlobal;
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}
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/// \returns If target supports ds_read/write_b128 and user enables generation
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/// of ds_read/write_b128.
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bool useDS128() const {
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return CIInsts && EnableDS128;
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}
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/// \returns If MUBUF instructions always perform range checking, even for
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/// buffer resources used for private memory access.
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bool privateMemoryResourceIsRangeChecked() const {
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return getGeneration() < AMDGPUSubtarget::GFX9;
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}
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bool hasAutoWaitcntBeforeBarrier() const {
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return AutoWaitcntBeforeBarrier;
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}
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bool hasCodeObjectV3() const {
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return CodeObjectV3;
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}
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bool hasUnalignedBufferAccess() const {
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return UnalignedBufferAccess;
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}
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bool hasUnalignedScratchAccess() const {
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return UnalignedScratchAccess;
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}
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bool hasApertureRegs() const {
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return HasApertureRegs;
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}
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bool isTrapHandlerEnabled() const {
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return TrapHandler;
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}
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bool isXNACKEnabled() const {
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return EnableXNACK;
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}
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bool hasFlatAddressSpace() const {
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return FlatAddressSpace;
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}
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bool hasFlatInstOffsets() const {
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return FlatInstOffsets;
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}
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bool hasFlatGlobalInsts() const {
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return FlatGlobalInsts;
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}
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bool hasFlatScratchInsts() const {
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return FlatScratchInsts;
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}
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bool hasFlatLgkmVMemCountInOrder() const {
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return getGeneration() > GFX9;
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}
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bool hasD16LoadStore() const {
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return getGeneration() >= GFX9;
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}
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/// Return if most LDS instructions have an m0 use that require m0 to be
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/// iniitalized.
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bool ldsRequiresM0Init() const {
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return getGeneration() < GFX9;
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}
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bool hasAddNoCarry() const {
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return AddNoCarryInsts;
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}
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bool hasUnpackedD16VMem() const {
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return HasUnpackedD16VMem;
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}
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bool isMesaKernel(const Function &F) const {
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return isMesa3DOS() && !AMDGPU::isShader(F.getCallingConv());
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}
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// Covers VS/PS/CS graphics shaders
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bool isMesaGfxShader(const Function &F) const {
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return isMesa3DOS() && AMDGPU::isShader(F.getCallingConv());
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}
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bool isAmdCodeObjectV2(const Function &F) const {
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return isAmdHsaOS() || isMesaKernel(F);
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}
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bool hasMad64_32() const {
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return getGeneration() >= SEA_ISLANDS;
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}
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bool hasFminFmaxLegacy() const {
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return getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS;
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}
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bool hasSDWA() const {
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return HasSDWA;
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}
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bool hasSDWAOmod() const {
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return HasSDWAOmod;
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}
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bool hasSDWAScalar() const {
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return HasSDWAScalar;
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}
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bool hasSDWASdst() const {
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return HasSDWASdst;
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}
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bool hasSDWAMac() const {
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return HasSDWAMac;
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}
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bool hasSDWAOutModsVOPC() const {
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return HasSDWAOutModsVOPC;
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}
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bool vmemWriteNeedsExpWaitcnt() const {
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return getGeneration() < SEA_ISLANDS;
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}
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bool hasDLInsts() const {
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return HasDLInsts;
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}
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bool d16PreservesUnusedBits() const {
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return D16PreservesUnusedBits;
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}
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/// Returns the offset in bytes from the start of the input buffer
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/// of the first explicit kernel argument.
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unsigned getExplicitKernelArgOffset(const Function &F) const {
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return isAmdCodeObjectV2(F) ? 0 : 36;
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}
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unsigned getAlignmentForImplicitArgPtr() const {
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return isAmdHsaOS() ? 8 : 4;
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}
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/// \returns Number of bytes of arguments that are passed to a shader or
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/// kernel in addition to the explicit ones declared for the function.
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unsigned getImplicitArgNumBytes(const Function &F) const {
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if (isMesaKernel(F))
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return 16;
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return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0);
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}
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// Scratch is allocated in 256 dword per wave blocks for the entire
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// wavefront. When viewed from the perspecive of an arbitrary workitem, this
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// is 4-byte aligned.
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//
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// Only 4-byte alignment is really needed to access anything. Transformations
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// on the pointer value itself may rely on the alignment / known low bits of
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// the pointer. Set this to something above the minimum to avoid needing
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// dynamic realignment in common cases.
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unsigned getStackAlignment() const {
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return 16;
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}
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bool enableMachineScheduler() const override {
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return true;
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}
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bool enableSubRegLiveness() const override {
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return true;
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}
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void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b;}
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bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal;}
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|
|
|
/// \returns Number of execution units per compute unit supported by the
|
|
/// subtarget.
|
|
unsigned getEUsPerCU() const {
|
|
return AMDGPU::IsaInfo::getEUsPerCU(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Maximum number of work groups per compute unit supported by the
|
|
/// subtarget and limited by given \p FlatWorkGroupSize.
|
|
unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const {
|
|
return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(getFeatureBits(),
|
|
FlatWorkGroupSize);
|
|
}
|
|
|
|
/// \returns Maximum number of waves per compute unit supported by the
|
|
/// subtarget without any kind of limitation.
|
|
unsigned getMaxWavesPerCU() const {
|
|
return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Maximum number of waves per compute unit supported by the
|
|
/// subtarget and limited by given \p FlatWorkGroupSize.
|
|
unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
|
|
return AMDGPU::IsaInfo::getMaxWavesPerCU(getFeatureBits(),
|
|
FlatWorkGroupSize);
|
|
}
|
|
|
|
/// \returns Minimum number of waves per execution unit supported by the
|
|
/// subtarget.
|
|
unsigned getMinWavesPerEU() const {
|
|
return AMDGPU::IsaInfo::getMinWavesPerEU(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Maximum number of waves per execution unit supported by the
|
|
/// subtarget without any kind of limitation.
|
|
unsigned getMaxWavesPerEU() const {
|
|
return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Maximum number of waves per execution unit supported by the
|
|
/// subtarget and limited by given \p FlatWorkGroupSize.
|
|
unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const {
|
|
return AMDGPU::IsaInfo::getMaxWavesPerEU(getFeatureBits(),
|
|
FlatWorkGroupSize);
|
|
}
|
|
|
|
/// \returns Minimum flat work group size supported by the subtarget.
|
|
unsigned getMinFlatWorkGroupSize() const {
|
|
return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Maximum flat work group size supported by the subtarget.
|
|
unsigned getMaxFlatWorkGroupSize() const {
|
|
return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Number of waves per work group supported by the subtarget and
|
|
/// limited by given \p FlatWorkGroupSize.
|
|
unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
|
|
return AMDGPU::IsaInfo::getWavesPerWorkGroup(getFeatureBits(),
|
|
FlatWorkGroupSize);
|
|
}
|
|
|
|
/// \returns Default range flat work group size for a calling convention.
|
|
std::pair<unsigned, unsigned> getDefaultFlatWorkGroupSize(CallingConv::ID CC) const;
|
|
|
|
/// \returns Subtarget's default pair of minimum/maximum flat work group sizes
|
|
/// for function \p F, or minimum/maximum flat work group sizes explicitly
|
|
/// requested using "amdgpu-flat-work-group-size" attribute attached to
|
|
/// function \p F.
|
|
///
|
|
/// \returns Subtarget's default values if explicitly requested values cannot
|
|
/// be converted to integer, or violate subtarget's specifications.
|
|
std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
|
|
|
|
/// \returns Subtarget's default pair of minimum/maximum number of waves per
|
|
/// execution unit for function \p F, or minimum/maximum number of waves per
|
|
/// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
|
|
/// attached to function \p F.
|
|
///
|
|
/// \returns Subtarget's default values if explicitly requested values cannot
|
|
/// be converted to integer, violate subtarget's specifications, or are not
|
|
/// compatible with minimum/maximum number of waves limited by flat work group
|
|
/// size, register usage, and/or lds usage.
|
|
std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
|
|
|
|
/// Creates value range metadata on an workitemid.* inrinsic call or load.
|
|
bool makeLIDRangeMetadata(Instruction *I) const;
|
|
};
|
|
|
|
class R600Subtarget final : public AMDGPUSubtarget {
|
|
private:
|
|
R600InstrInfo InstrInfo;
|
|
R600FrameLowering FrameLowering;
|
|
R600TargetLowering TLInfo;
|
|
|
|
public:
|
|
R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
|
|
const TargetMachine &TM);
|
|
|
|
const R600InstrInfo *getInstrInfo() const override {
|
|
return &InstrInfo;
|
|
}
|
|
|
|
const R600FrameLowering *getFrameLowering() const override {
|
|
return &FrameLowering;
|
|
}
|
|
|
|
const R600TargetLowering *getTargetLowering() const override {
|
|
return &TLInfo;
|
|
}
|
|
|
|
const R600RegisterInfo *getRegisterInfo() const override {
|
|
return &InstrInfo.getRegisterInfo();
|
|
}
|
|
|
|
bool hasCFAluBug() const {
|
|
return CFALUBug;
|
|
}
|
|
|
|
bool hasVertexCache() const {
|
|
return HasVertexCache;
|
|
}
|
|
|
|
short getTexVTXClauseSize() const {
|
|
return TexVTXClauseSize;
|
|
}
|
|
};
|
|
|
|
class SISubtarget final : public AMDGPUSubtarget {
|
|
private:
|
|
SIInstrInfo InstrInfo;
|
|
SIFrameLowering FrameLowering;
|
|
SITargetLowering TLInfo;
|
|
|
|
/// GlobalISel related APIs.
|
|
std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
|
|
std::unique_ptr<InstructionSelector> InstSelector;
|
|
std::unique_ptr<LegalizerInfo> Legalizer;
|
|
std::unique_ptr<RegisterBankInfo> RegBankInfo;
|
|
|
|
public:
|
|
SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
|
|
const GCNTargetMachine &TM);
|
|
|
|
const SIInstrInfo *getInstrInfo() const override {
|
|
return &InstrInfo;
|
|
}
|
|
|
|
const SIFrameLowering *getFrameLowering() const override {
|
|
return &FrameLowering;
|
|
}
|
|
|
|
const SITargetLowering *getTargetLowering() const override {
|
|
return &TLInfo;
|
|
}
|
|
|
|
const CallLowering *getCallLowering() const override {
|
|
return CallLoweringInfo.get();
|
|
}
|
|
|
|
const InstructionSelector *getInstructionSelector() const override {
|
|
return InstSelector.get();
|
|
}
|
|
|
|
const LegalizerInfo *getLegalizerInfo() const override {
|
|
return Legalizer.get();
|
|
}
|
|
|
|
const RegisterBankInfo *getRegBankInfo() const override {
|
|
return RegBankInfo.get();
|
|
}
|
|
|
|
const SIRegisterInfo *getRegisterInfo() const override {
|
|
return &InstrInfo.getRegisterInfo();
|
|
}
|
|
|
|
// XXX - Why is this here if it isn't in the default pass set?
|
|
bool enableEarlyIfConversion() const override {
|
|
return true;
|
|
}
|
|
|
|
void overrideSchedPolicy(MachineSchedPolicy &Policy,
|
|
unsigned NumRegionInstrs) const override;
|
|
|
|
bool isVGPRSpillingEnabled(const Function& F) const;
|
|
|
|
unsigned getMaxNumUserSGPRs() const {
|
|
return 16;
|
|
}
|
|
|
|
bool hasSMemRealTime() const {
|
|
return HasSMemRealTime;
|
|
}
|
|
|
|
bool hasMovrel() const {
|
|
return HasMovrel;
|
|
}
|
|
|
|
bool hasVGPRIndexMode() const {
|
|
return HasVGPRIndexMode;
|
|
}
|
|
|
|
bool useVGPRIndexMode(bool UserEnable) const {
|
|
return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
|
|
}
|
|
|
|
bool hasScalarCompareEq64() const {
|
|
return getGeneration() >= VOLCANIC_ISLANDS;
|
|
}
|
|
|
|
bool hasScalarStores() const {
|
|
return HasScalarStores;
|
|
}
|
|
|
|
bool hasScalarAtomics() const {
|
|
return HasScalarAtomics;
|
|
}
|
|
|
|
bool hasInv2PiInlineImm() const {
|
|
return HasInv2PiInlineImm;
|
|
}
|
|
|
|
bool hasDPP() const {
|
|
return HasDPP;
|
|
}
|
|
|
|
bool enableSIScheduler() const {
|
|
return EnableSIScheduler;
|
|
}
|
|
|
|
bool debuggerSupported() const {
|
|
return debuggerInsertNops() && debuggerReserveRegs() &&
|
|
debuggerEmitPrologue();
|
|
}
|
|
|
|
bool debuggerInsertNops() const {
|
|
return DebuggerInsertNops;
|
|
}
|
|
|
|
bool debuggerReserveRegs() const {
|
|
return DebuggerReserveRegs;
|
|
}
|
|
|
|
bool debuggerEmitPrologue() const {
|
|
return DebuggerEmitPrologue;
|
|
}
|
|
|
|
bool loadStoreOptEnabled() const {
|
|
return EnableLoadStoreOpt;
|
|
}
|
|
|
|
bool hasSGPRInitBug() const {
|
|
return SGPRInitBug;
|
|
}
|
|
|
|
bool has12DWordStoreHazard() const {
|
|
return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
|
|
}
|
|
|
|
bool hasSMovFedHazard() const {
|
|
return getGeneration() >= AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
bool hasReadM0MovRelInterpHazard() const {
|
|
return getGeneration() >= AMDGPUSubtarget::GFX9;
|
|
}
|
|
|
|
bool hasReadM0SendMsgHazard() const {
|
|
return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
|
|
}
|
|
|
|
unsigned getKernArgSegmentSize(const Function &F,
|
|
unsigned ExplictArgBytes) const;
|
|
|
|
/// Return the maximum number of waves per SIMD for kernels using \p SGPRs SGPRs
|
|
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
|
|
|
|
/// Return the maximum number of waves per SIMD for kernels using \p VGPRs VGPRs
|
|
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
|
|
|
|
/// \returns true if the flat_scratch register should be initialized with the
|
|
/// pointer to the wave's scratch memory rather than a size and offset.
|
|
bool flatScratchIsPointer() const {
|
|
return getGeneration() >= GFX9;
|
|
}
|
|
|
|
/// \returns true if the machine has merged shaders in which s0-s7 are
|
|
/// reserved by the hardware and user SGPRs start at s8
|
|
bool hasMergedShaders() const {
|
|
return getGeneration() >= GFX9;
|
|
}
|
|
|
|
/// \returns SGPR allocation granularity supported by the subtarget.
|
|
unsigned getSGPRAllocGranule() const {
|
|
return AMDGPU::IsaInfo::getSGPRAllocGranule(getFeatureBits());
|
|
}
|
|
|
|
/// \returns SGPR encoding granularity supported by the subtarget.
|
|
unsigned getSGPREncodingGranule() const {
|
|
return AMDGPU::IsaInfo::getSGPREncodingGranule(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Total number of SGPRs supported by the subtarget.
|
|
unsigned getTotalNumSGPRs() const {
|
|
return AMDGPU::IsaInfo::getTotalNumSGPRs(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Addressable number of SGPRs supported by the subtarget.
|
|
unsigned getAddressableNumSGPRs() const {
|
|
return AMDGPU::IsaInfo::getAddressableNumSGPRs(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Minimum number of SGPRs that meets the given number of waves per
|
|
/// execution unit requirement supported by the subtarget.
|
|
unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
|
|
return AMDGPU::IsaInfo::getMinNumSGPRs(getFeatureBits(), WavesPerEU);
|
|
}
|
|
|
|
/// \returns Maximum number of SGPRs that meets the given number of waves per
|
|
/// execution unit requirement supported by the subtarget.
|
|
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
|
|
return AMDGPU::IsaInfo::getMaxNumSGPRs(getFeatureBits(), WavesPerEU,
|
|
Addressable);
|
|
}
|
|
|
|
/// \returns Reserved number of SGPRs for given function \p MF.
|
|
unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
|
|
|
|
/// \returns Maximum number of SGPRs that meets number of waves per execution
|
|
/// unit requirement for function \p MF, or number of SGPRs explicitly
|
|
/// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
|
|
///
|
|
/// \returns Value that meets number of waves per execution unit requirement
|
|
/// if explicitly requested value cannot be converted to integer, violates
|
|
/// subtarget's specifications, or does not meet number of waves per execution
|
|
/// unit requirement.
|
|
unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
|
|
|
|
/// \returns VGPR allocation granularity supported by the subtarget.
|
|
unsigned getVGPRAllocGranule() const {
|
|
return AMDGPU::IsaInfo::getVGPRAllocGranule(getFeatureBits());
|
|
}
|
|
|
|
/// \returns VGPR encoding granularity supported by the subtarget.
|
|
unsigned getVGPREncodingGranule() const {
|
|
return AMDGPU::IsaInfo::getVGPREncodingGranule(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Total number of VGPRs supported by the subtarget.
|
|
unsigned getTotalNumVGPRs() const {
|
|
return AMDGPU::IsaInfo::getTotalNumVGPRs(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Addressable number of VGPRs supported by the subtarget.
|
|
unsigned getAddressableNumVGPRs() const {
|
|
return AMDGPU::IsaInfo::getAddressableNumVGPRs(getFeatureBits());
|
|
}
|
|
|
|
/// \returns Minimum number of VGPRs that meets given number of waves per
|
|
/// execution unit requirement supported by the subtarget.
|
|
unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
|
|
return AMDGPU::IsaInfo::getMinNumVGPRs(getFeatureBits(), WavesPerEU);
|
|
}
|
|
|
|
/// \returns Maximum number of VGPRs that meets given number of waves per
|
|
/// execution unit requirement supported by the subtarget.
|
|
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
|
|
return AMDGPU::IsaInfo::getMaxNumVGPRs(getFeatureBits(), WavesPerEU);
|
|
}
|
|
|
|
/// \returns Reserved number of VGPRs for given function \p MF.
|
|
unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
|
|
return debuggerReserveRegs() ? 4 : 0;
|
|
}
|
|
|
|
/// \returns Maximum number of VGPRs that meets number of waves per execution
|
|
/// unit requirement for function \p MF, or number of VGPRs explicitly
|
|
/// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
|
|
///
|
|
/// \returns Value that meets number of waves per execution unit requirement
|
|
/// if explicitly requested value cannot be converted to integer, violates
|
|
/// subtarget's specifications, or does not meet number of waves per execution
|
|
/// unit requirement.
|
|
unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
|
|
|
|
void getPostRAMutations(
|
|
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
|
|
const override;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
|