llvm-project/llvm/test/CodeGen/AArch64/rmif-use-nzcv.mir

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# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
# CHECK: [[@LINE+10]]:45: missing implicit register operand 'implicit-def $nzcv'
...
---
name: test_flags
liveins:
- { reg: '$x0' }
body: |
bb.0:
liveins: $x0
RMIF renamable $x0, 0, 0, implicit $nzcv
RET undef $lr, implicit killed $w0