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AArch64
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[LegalizeTypes] Legalize vector rotate operations
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2020-10-24 11:30:32 +01:00 |
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AMDGPU
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AMDGPU: Increase branch size estimate with offset bug
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2020-10-23 10:34:24 -04:00 |
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ARC
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ARM
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[PrologEpilogInserter] Reduce PR16393 test and fix a prologue parameter in a debuginfo test
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2020-10-18 22:18:42 -07:00 |
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AVR
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[AVR] fix interrupt stack pointer restoration
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2020-10-01 18:52:13 +13:00 |
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BPF
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[BPF] Make BPFAbstractMemberAccessPass required
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2020-10-09 11:26:37 -07:00 |
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Generic
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[llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics.
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2020-10-07 10:36:44 -07:00 |
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Hexagon
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[Hexagon] Handle selection between HVX vector predicates
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2020-10-23 18:22:03 -05:00 |
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Inputs
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Lanai
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MIR
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Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"
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2020-09-29 15:33:34 +02:00 |
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MSP430
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…
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Mips
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[DAG][ARM][MIPS][RISCV] Improve funnel shift promotion to use 'double shift' patterns
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2020-10-12 14:11:02 +01:00 |
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NVPTX
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[TargetLowering] Check boolean content when folding bit compare
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2020-10-21 11:46:55 +01:00 |
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PowerPC
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[PowerPC] Add intrinsics for MMA
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2020-10-23 13:16:02 -05:00 |
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RISCV
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[RISCV][NFC] Add more tests for 32-bit constant materialization
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2020-10-22 11:36:34 +01:00 |
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SPARC
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[Sparc] Remove cast that truncates immediate operands to 32 bits.
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2020-10-02 20:14:55 -04:00 |
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SystemZ
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[SystemZ] Define MaxInstLength to have the value of 6.
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2020-10-24 09:19:34 +02:00 |
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Thumb
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Thumb2
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Revert "[ARM][LowOverheadLoops] Adjust Start insertion."
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2020-10-20 08:55:21 +01:00 |
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VE
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[VE] Add setcc for fp128
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2020-10-19 21:36:57 +09:00 |
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WebAssembly
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[WebAssembly] Prototype i8x16.popcnt
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2020-10-15 21:18:22 +00:00 |
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WinCFGuard
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Reland [CFGuard] Add address-taken IAT tables and delay-load support
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2020-10-13 13:20:52 -07:00 |
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WinEH
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X86
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[X86] Add a stub for Intel's alderlake.
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2020-10-24 19:01:22 +02:00 |
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XCore
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