forked from OSchip/llvm-project
101 lines
3.7 KiB
LLVM
101 lines
3.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
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; GCN-LABEL: {{^}}fneg_fabs_fadd_f16:
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; CI: v_cvt_f32_f16_e32
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; CI: v_cvt_f32_f16_e64 [[CVT_ABS_X:v[0-9]+]], |v{{[0-9]+}}|
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; CI: v_subrev_f32_e32 v{{[0-9]+}}, [[CVT_ABS_X]], v{{[0-9]+}}
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; VI-NOT: and
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; VI: v_sub_f16_e64 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|
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define void @fneg_fabs_fadd_f16(half addrspace(1)* %out, half %x, half %y) {
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%fabs = call half @llvm.fabs.f16(half %x)
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%fsub = fsub half -0.000000e+00, %fabs
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%fadd = fadd half %y, %fsub
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store half %fadd, half addrspace(1)* %out, align 2
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_fmul_f16:
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; CI-DAG: v_cvt_f32_f16_e32
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; CI-DAG: v_cvt_f32_f16_e64 [[CVT_NEG_ABS_X:v[0-9]+]], -|{{v[0-9]+}}|
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; CI: v_mul_f32_e32 {{v[0-9]+}}, [[CVT_NEG_ABS_X]], {{v[0-9]+}}
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; CI: v_cvt_f16_f32_e32
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; VI-NOT: and
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; VI: v_mul_f16_e64 [[MUL:v[0-9]+]], {{v[0-9]+}}, -|{{v[0-9]+}}|
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; VI-NOT: [[MUL]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
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define void @fneg_fabs_fmul_f16(half addrspace(1)* %out, half %x, half %y) {
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%fabs = call half @llvm.fabs.f16(half %x)
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%fsub = fsub half -0.000000e+00, %fabs
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%fmul = fmul half %y, %fsub
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store half %fmul, half addrspace(1)* %out, align 2
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ret void
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}
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; DAGCombiner will transform:
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; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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; GCN-LABEL: {{^}}fneg_fabs_free_f16:
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; GCN: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}}
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define void @fneg_fabs_free_f16(half addrspace(1)* %out, i16 %in) {
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%bc = bitcast i16 %in to half
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%fabs = call half @llvm.fabs.f16(half %bc)
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%fsub = fsub half -0.000000e+00, %fabs
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store half %fsub, half addrspace(1)* %out
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ret void
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}
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; FIXME: Should use or
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; GCN-LABEL: {{^}}fneg_fabs_f16:
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; GCN: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}}
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define void @fneg_fabs_f16(half addrspace(1)* %out, half %in) {
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%fabs = call half @llvm.fabs.f16(half %in)
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%fsub = fsub half -0.000000e+00, %fabs
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store half %fsub, half addrspace(1)* %out, align 2
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_fabs_f16:
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; GCN: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}}
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define void @v_fneg_fabs_f16(half addrspace(1)* %out, half addrspace(1)* %in) {
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%val = load half, half addrspace(1)* %in, align 2
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%fabs = call half @llvm.fabs.f16(half %val)
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%fsub = fsub half -0.000000e+00, %fabs
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store half %fsub, half addrspace(1)* %out, align 2
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ret void
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}
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; FIXME: single bit op
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; GCN-LABEL: {{^}}fneg_fabs_v2f16:
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; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}}
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; GCN: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
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; GCN: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
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; GCN: store_dword
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define void @fneg_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) {
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%fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
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%fsub = fsub <2 x half> <half -0.000000e+00, half -0.000000e+00>, %fabs
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store <2 x half> %fsub, <2 x half> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fneg_fabs_v4f16:
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; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x8000{{$}}
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; GCN: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
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; GCN: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
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; GCN: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
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; GCN: v_or_b32_e32 v{{[0-9]+}}, [[MASK]],
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; GCN: store_dwordx2
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define void @fneg_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) {
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%fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in)
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%fsub = fsub <4 x half> <half -0.000000e+00, half -0.000000e+00, half -0.000000e+00, half -0.000000e+00>, %fabs
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store <4 x half> %fsub, <4 x half> addrspace(1)* %out
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ret void
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}
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declare half @llvm.fabs.f16(half) readnone
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declare <2 x half> @llvm.fabs.v2f16(<2 x half>) readnone
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declare <4 x half> @llvm.fabs.v4f16(<4 x half>) readnone
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