forked from OSchip/llvm-project
513 lines
16 KiB
YAML
513 lines
16 KiB
YAML
# RUN: llc -verify-machineinstrs -march=amdgcn -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
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# Check that add with carry out isn't incorrectly reduced to e32 when
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# the carry out is a virtual register.
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# TODO: We should run this test until the end of codegen to make sure
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# that the post-RA run does manage to shrink it, but right now the
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# resume crashes
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...
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# GCN-LABEL: name: shrink_add_vop3{{$}}
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# GCN: %29, %9 = V_ADD_I32_e64 %19, %17, implicit %exec
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# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
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name: shrink_add_vop3
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32_xm0 }
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- { id: 9, class: sreg_64 }
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- { id: 10, class: sreg_32_xm0 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sgpr_64 }
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- { id: 13, class: sgpr_128 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_64 }
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- { id: 16, class: sgpr_128 }
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- { id: 17, class: vgpr_32 }
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- { id: 18, class: vreg_64 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: sreg_32_xm0 }
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- { id: 22, class: sreg_32 }
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- { id: 23, class: sreg_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vreg_64 }
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- { id: 26, class: vgpr_32 }
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- { id: 27, class: vreg_64 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vgpr_32 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
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%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%27 = REG_SEQUENCE %3, 1, %26, 2
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%10 = S_MOV_B32 61440
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%11 = S_MOV_B32 0
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%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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%13 = REG_SEQUENCE killed %5, 17, %12, 18
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%28 = V_LSHL_B64 killed %27, 2, implicit %exec
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%16 = REG_SEQUENCE killed %4, 17, %12, 18
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%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
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%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
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%29, %9 = V_ADD_I32_e64 %19, %17, implicit %exec
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%24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
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BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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---
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# GCN-LABEL: name: shrink_sub_vop3{{$}}
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# GCN: %29, %9 = V_SUB_I32_e64 %19, %17, implicit %exec
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# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
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name: shrink_sub_vop3
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32_xm0 }
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- { id: 9, class: sreg_64 }
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- { id: 10, class: sreg_32_xm0 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sgpr_64 }
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- { id: 13, class: sgpr_128 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_64 }
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- { id: 16, class: sgpr_128 }
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- { id: 17, class: vgpr_32 }
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- { id: 18, class: vreg_64 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: sreg_32_xm0 }
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- { id: 22, class: sreg_32 }
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- { id: 23, class: sreg_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vreg_64 }
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- { id: 26, class: vgpr_32 }
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- { id: 27, class: vreg_64 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vgpr_32 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
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%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%27 = REG_SEQUENCE %3, 1, %26, 2
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%10 = S_MOV_B32 61440
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%11 = S_MOV_B32 0
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%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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%13 = REG_SEQUENCE killed %5, 17, %12, 18
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%28 = V_LSHL_B64 killed %27, 2, implicit %exec
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%16 = REG_SEQUENCE killed %4, 17, %12, 18
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%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
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%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
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%29, %9 = V_SUB_I32_e64 %19, %17, implicit %exec
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%24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
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BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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---
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# GCN-LABEL: name: shrink_subrev_vop3{{$}}
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# GCN: %29, %9 = V_SUBREV_I32_e64 %19, %17, implicit %exec
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# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
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name: shrink_subrev_vop3
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32_xm0 }
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- { id: 9, class: sreg_64 }
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- { id: 10, class: sreg_32_xm0 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sgpr_64 }
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- { id: 13, class: sgpr_128 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_64 }
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- { id: 16, class: sgpr_128 }
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- { id: 17, class: vgpr_32 }
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- { id: 18, class: vreg_64 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: sreg_32_xm0 }
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- { id: 22, class: sreg_32 }
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- { id: 23, class: sreg_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vreg_64 }
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- { id: 26, class: vgpr_32 }
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- { id: 27, class: vreg_64 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vgpr_32 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
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%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%27 = REG_SEQUENCE %3, 1, %26, 2
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%10 = S_MOV_B32 61440
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%11 = S_MOV_B32 0
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%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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%13 = REG_SEQUENCE killed %5, 17, %12, 18
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%28 = V_LSHL_B64 killed %27, 2, implicit %exec
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%16 = REG_SEQUENCE killed %4, 17, %12, 18
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%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
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%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
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%29, %9 = V_SUBREV_I32_e64 %19, %17, implicit %exec
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%24 = V_CNDMASK_B32_e64 0, 1, killed %9, implicit %exec
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BUFFER_STORE_DWORD_ADDR64 %29, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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---
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# GCN-LABEL: name: check_addc_src2_vop3{{$}}
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# GCN: %29, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
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# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
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name: check_addc_src2_vop3
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32_xm0 }
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- { id: 9, class: sreg_64 }
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- { id: 10, class: sreg_32_xm0 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sgpr_64 }
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- { id: 13, class: sgpr_128 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_64 }
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- { id: 16, class: sgpr_128 }
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- { id: 17, class: vgpr_32 }
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- { id: 18, class: vreg_64 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: sreg_32_xm0 }
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- { id: 22, class: sreg_32 }
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- { id: 23, class: sreg_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vreg_64 }
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- { id: 26, class: vgpr_32 }
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- { id: 27, class: vreg_64 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vgpr_32 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0:
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liveins: %sgpr0_sgpr1, %vgpr0
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%3 = COPY %vgpr0
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%0 = COPY %sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
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%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
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%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
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%27 = REG_SEQUENCE %3, 1, %26, 2
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%10 = S_MOV_B32 61440
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%11 = S_MOV_B32 0
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%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
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%13 = REG_SEQUENCE killed %5, 17, %12, 18
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%28 = V_LSHL_B64 killed %27, 2, implicit %exec
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%16 = REG_SEQUENCE killed %4, 17, %12, 18
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%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
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%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
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%9 = S_MOV_B64 0
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%29, %vcc = V_ADDC_U32_e64 %19, %17, %9, implicit %exec
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%24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
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BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
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S_ENDPGM
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...
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---
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# GCN-LABEL: name: shrink_addc_vop3{{$}}
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# GCN: %29 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit %vcc, implicit %exec
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# GCN %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
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name: shrink_addc_vop3
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alignment: 0
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_64_xexec }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32_xm0 }
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- { id: 9, class: sreg_64 }
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- { id: 10, class: sreg_32_xm0 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sgpr_64 }
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- { id: 13, class: sgpr_128 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_64 }
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- { id: 16, class: sgpr_128 }
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- { id: 17, class: vgpr_32 }
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- { id: 18, class: vreg_64 }
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- { id: 19, class: vgpr_32 }
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- { id: 20, class: vreg_64 }
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- { id: 21, class: sreg_32_xm0 }
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- { id: 22, class: sreg_32 }
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- { id: 23, class: sreg_32 }
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- { id: 24, class: vgpr_32 }
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- { id: 25, class: vreg_64 }
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- { id: 26, class: vgpr_32 }
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- { id: 27, class: vreg_64 }
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- { id: 28, class: vreg_64 }
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- { id: 29, class: vgpr_32 }
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liveins:
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- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '%vgpr0', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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|
bb.0:
|
|
liveins: %sgpr0_sgpr1, %vgpr0
|
|
|
|
%3 = COPY %vgpr0
|
|
%0 = COPY %sgpr0_sgpr1
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
%10 = S_MOV_B32 61440
|
|
%11 = S_MOV_B32 0
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit %exec
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
|
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
|
|
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
|
|
%vcc = S_MOV_B64 0
|
|
%29, %vcc = V_ADDC_U32_e64 %19, %17, %vcc, implicit %exec
|
|
%24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
|
|
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
|
|
S_ENDPGM
|
|
|
|
...
|
|
|
|
---
|
|
# GCN-LABEL: name: shrink_addc_undef_vcc{{$}}
|
|
# GCN: %29 = V_ADDC_U32_e32 %19, %17, implicit-def %vcc, implicit undef %vcc, implicit %exec
|
|
# GCN: %24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
|
|
name: shrink_addc_undef_vcc
|
|
alignment: 0
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: sgpr_64 }
|
|
- { id: 1, class: sreg_32_xm0 }
|
|
- { id: 2, class: sgpr_32 }
|
|
- { id: 3, class: vgpr_32 }
|
|
- { id: 4, class: sreg_64_xexec }
|
|
- { id: 5, class: sreg_64_xexec }
|
|
- { id: 6, class: sreg_32 }
|
|
- { id: 7, class: sreg_32 }
|
|
- { id: 8, class: sreg_32_xm0 }
|
|
- { id: 9, class: sreg_64 }
|
|
- { id: 10, class: sreg_32_xm0 }
|
|
- { id: 11, class: sreg_32_xm0 }
|
|
- { id: 12, class: sgpr_64 }
|
|
- { id: 13, class: sgpr_128 }
|
|
- { id: 14, class: sreg_32_xm0 }
|
|
- { id: 15, class: sreg_64 }
|
|
- { id: 16, class: sgpr_128 }
|
|
- { id: 17, class: vgpr_32 }
|
|
- { id: 18, class: vreg_64 }
|
|
- { id: 19, class: vgpr_32 }
|
|
- { id: 20, class: vreg_64 }
|
|
- { id: 21, class: sreg_32_xm0 }
|
|
- { id: 22, class: sreg_32 }
|
|
- { id: 23, class: sreg_32 }
|
|
- { id: 24, class: vgpr_32 }
|
|
- { id: 25, class: vreg_64 }
|
|
- { id: 26, class: vgpr_32 }
|
|
- { id: 27, class: vreg_64 }
|
|
- { id: 28, class: vreg_64 }
|
|
- { id: 29, class: vgpr_32 }
|
|
liveins:
|
|
- { reg: '%sgpr0_sgpr1', virtual-reg: '%0' }
|
|
- { reg: '%vgpr0', virtual-reg: '%3' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
maxCallFrameSize: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
body: |
|
|
bb.0:
|
|
liveins: %sgpr0_sgpr1, %vgpr0
|
|
|
|
%3 = COPY %vgpr0
|
|
%0 = COPY %sgpr0_sgpr1
|
|
%4 = S_LOAD_DWORDX2_IMM %0, 9, 0
|
|
%5 = S_LOAD_DWORDX2_IMM %0, 11, 0
|
|
%26 = V_ASHRREV_I32_e32 31, %3, implicit %exec
|
|
%27 = REG_SEQUENCE %3, 1, %26, 2
|
|
%10 = S_MOV_B32 61440
|
|
%11 = S_MOV_B32 0
|
|
%12 = REG_SEQUENCE killed %11, 1, killed %10, 2
|
|
%13 = REG_SEQUENCE killed %5, 17, %12, 18
|
|
%28 = V_LSHL_B64 killed %27, 2, implicit %exec
|
|
%16 = REG_SEQUENCE killed %4, 17, %12, 18
|
|
%17 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 0, 0, 0, 0, implicit %exec
|
|
%19 = BUFFER_LOAD_DWORD_ADDR64 %28, %13, 0, 4, 0, 0, 0, implicit %exec
|
|
%29, %vcc = V_ADDC_U32_e64 %19, %17, undef %vcc, implicit %exec
|
|
%24 = V_CNDMASK_B32_e64 0, 1, killed %vcc, implicit %exec
|
|
BUFFER_STORE_DWORD_ADDR64 %24, %28, killed %16, 0, 0, 0, 0, 0, implicit %exec
|
|
S_ENDPGM
|
|
|
|
...
|