forked from OSchip/llvm-project
283 lines
11 KiB
LLVM
283 lines
11 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}system_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @system_unordered(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in unordered, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}system_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @system_monotonic(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in monotonic, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}system_acquire
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @system_acquire(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in acquire, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}system_seq_cst
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; CHECK: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @system_seq_cst(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in seq_cst, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_unordered(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") unordered, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_monotonic(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") monotonic, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_acquire
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_acquire(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") acquire, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}singlethread_seq_cst
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @singlethread_seq_cst(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") seq_cst, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}agent_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @agent_unordered(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") unordered, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}agent_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @agent_monotonic(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") monotonic, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}agent_acquire
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @agent_acquire(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") acquire, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}agent_seq_cst
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; CHECK: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NEXT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @agent_seq_cst(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") seq_cst, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @workgroup_unordered(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") unordered, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @workgroup_monotonic(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") monotonic, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_acquire
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @workgroup_acquire(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") acquire, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}workgroup_seq_cst
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @workgroup_seq_cst(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") seq_cst, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_unordered
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_unordered(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") unordered, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_monotonic
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_monotonic(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") monotonic, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_acquire
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_acquire(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") acquire, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}wavefront_seq_cst
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
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; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
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; CHECK-NOT: buffer_wbinvl1_vol
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; CHECK: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @wavefront_seq_cst(
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i32 addrspace(4)* %in, i32 addrspace(4)* %out) {
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entry:
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%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") seq_cst, align 4
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store i32 %val, i32 addrspace(4)* %out
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ret void
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}
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